Storage device and data writing method

Patent metadata

Field	Value
Publication number	US-12100448-B2
Application number	US-202117530128-A
Country	US
Kind code	B2
Filing date	Nov 18, 2021
Priority date	May 21, 2019
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

A storage device may be used in a neural network. The storage device includes a memristor unit, a current-controlled circuit, and a write circuit. The memristor unit has a structure of one-transistor and one-resistive random access memory (1T1R). The current-controlled circuit is configured to limit a current passing through the memristor unit to a target current, where the target current is determined based on target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The write circuit is configured to load a write voltage to the memristor unit in cooperation with the current-controlled circuit, to write the target data to the memristor unit.

First claim

What is claimed is:

1. A data writing method for writing data to a memristor unit having a one-transistor and one-resistive random access memory (1T1R) structure, the method comprising:
limiting, by a current-controlled circuit, a current passing through the memristor unit to a target current, wherein the target current is determined based on a target conductance of the memristor unit and a gate voltage of a transistor in the memristor unit, and the target conductance indicates target data to be written into the memristor unit; and
in cooperation with the current-controlled circuit, loading, by a write circuit, a write voltage to the memristor unit, to write the target data to the memristor unit;
wherein loading the write voltage to the memristor unit comprises loading a plurality of set pulses to the memristor unit, wherein first respective set pulses of the plurality of set pulses loaded to the memristor unit each decrease resistance of the memristor unit and increase the current passing through the memristor unit until the current passing through the memristor unit reaches the target current; and
wherein one or more second respective set pulses of the plurality of set pulses loaded to the memristor unit after the current passing through the memristor unit has reached the target current do not change conductance of the memristor unit.

2. The method according to claim 1 , wherein the target current I, the write voltage V b , the target conductance G, and a drain voltage V d of the transistor satisfy a formula

G
=

I

V
b

-

V
d

.

3. The data writing method according to claim 1 , wherein a quantity of set pulses and pulse widths for the plurality of set pulses is preconfigured based on a model of the memristor unit such that, after the memristor unit is loaded with the preconfigured quantity of set pulses, an initial conductance of the memristor unit is adjusted to the target conductance.

4. The data writing method according to claim 1 , further comprising:
in cooperation with the current-controlled circuit, loading, by the write circuit, a second write voltage to the memristor unit, to write second target data to the memristor unit;
wherein loading the second write voltage to the memristor unit comprises loading a plurality of reset pulses to the memristor unit, wherein first respective reset pulses of the plurality of reset pulses loaded to the memristor unit each increase resistance of the memristor unit and decrease the current passing through the memristor unit until the current passing through the memristor unit reaches a minimum target current; and
wherein one or more second respective reset pulses of the plurality of reset pulses loaded to the memristor unit after the current passing through the memristor unit has reached the minimum target current do not change conductance of the memristor unit.

5. The data writing method according to claim 4 , wherein a quantity of reset pulses and pulse widths for the plurality of reset pulses is preconfigured based on a model of the memristor unit such that, after the memristor unit is loaded with the preconfigured quantity of reset pulses, an initial conductance of the memristor unit is adjusted to the target conductance.

Assignees

• Huawei Tech Co Ltd
• Univ Tsinghua

Inventors

• Gao Bin
• Wang Kanwen
• Chen Junren
• Zhang Rui
• Wu Huaqiang

Classifications

• G06N3/065

  Analogue means · CPC title

• G11C2213/15

  Current-voltage curve · CPC title

• G11C2013/0078

  Write using current through the cell · CPC title

• G11C11/5685

  using storage elements comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title