Interrupt signaling for a memory device

Patent metadata

Field	Value
Publication number	US-12099746-B2
Application number	US-202017116180-A
Country	US
Kind code	B2
Filing date	Dec 9, 2020
Priority date	Dec 16, 2019
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

Methods, systems, and devices for interrupt signaling for a memory device are described. A memory device may transmit an interrupt signal to a host device to alter a sequence of operations that would otherwise be executed by the host device. The memory device may transmit the interrupt signal in response to detecting an error condition at the memory device, a performance degradation at the memory device, or another trigger event. In some examples, the memory device may include a dedicated interrupt pin for transmitting interrupt signals. Alternatively, the memory device may transmit interrupt signals via a pin also sued to transmit error detection codes. For example, the memory device may transmit an interrupt signal before or after an error detection code or may invert the error detection code to indicate the interrupt, in which case the inverted error detection code may act as an interrupt signal.

First claim

What is claimed is:

1. A method, comprising:
receiving, at a memory device, a read command for data stored at the memory device;
transmitting, based at least in part on receiving the read command, the data via a first interface;
generating, based at least in part on the read command, an error detection code for the data;
transmitting, based at least in part on receiving the read command, an indication of an interrupt via a second interface, wherein the indication of the interrupt comprises a bitwise inversion of the error detection code;
receiving, after transmitting the indication of the interrupt via the second interface, a request for information via a third interface; and
transmitting, based at least in part on the request, an indication of a value of an operating parameter for the memory device via the third interface, wherein the value of the operating parameter is indicative of an operational condition associated with the memory device, and wherein the operating parameter comprises a voltage, a temperature, a status of one or more fuses, a PLL status, or a flag indicating an operability of the memory device.

2. The method of claim 1 , wherein the indication of the interrupt is transmitted via the second interface after at least a portion of the data is transmitted via the first interface.

3. The method of claim 1 , wherein the second interface comprises an error detection code (EDC) pin.

4. The method of claim 1 , wherein the second interface comprises a pin dedicated to carrying indications of interrupts.

5. The method of claim 1 , wherein the third interface comprises a Joint Test Action Group (JTAG) interface.

6. The method of claim 1 , wherein the interrupt is configured to alter a sequence of operations by a host device for the memory device.

7. The method of claim 1 , wherein the first interface comprises a data interface.

8. A method, comprising:
transmitting, to a memory device, a read command for data;
receiving, based at least in part on the read command, the data via a first interface;
receiving, based at least in part on the read command, an indication of an interrupt via a second interface;
determining whether the indication of the interrupt comprises a bitwise inversion of an error detection code associated with the data;
altering a sequence of operations based at least in part on determining that the indication of the interrupt comprises the bitwise inversion of the error detection code;
transmitting, after receiving the indication of the interrupt via the second interface and based at least in part on altering the sequence of operations, a request for information via a third interface; and
receiving, based at least in part on the request, an indication of a value of an operating parameter for the memory device via the third interface, wherein the value of the operating parameter is indicative of an operational condition associated with the memory device, and wherein the operating parameter comprises a voltage, a temperature, a status of one or more fuses, a PLL status, or a flag indicating an operability of the memory device.

9. The method of claim 8 , wherein the indication of the interrupt is received via the second interface after at least a portion of the data is received via the first interface.

10. The method of claim 8 , wherein the second interface comprises an error detection code pin, or wherein the second interface comprises a pin dedicated to carrying indications of interrupts.

11. A memory system, comprising:
one or more memory arrays operable to store data;
a command address interface operable to receive an access command associated with the data;
a data interface operable to exchange the data with the one or more memory arrays;
a third interface operable to transmit an indication of an interrupt based at least in part on the access command and a condition of the memory system;
an error detection component coupled with the third interface and operable to determine an error detection code for the data, wherein the third interface comprises an error detection code pin;
an interrupt component coupled with the error detection code pin and operable to transmit a signal via the error detection code pin, the signal comprising the indication of the interrupt, wherein the indication of the interrupt comprises a bitwise inversion of the error detection code;
a fourth interface operable to receive, after transmission of the indication of the interrupt via the third interface, a request for information; and
the fourth interface further operable to transmit, based at least in part on the request, an indication of a value of an operating parameter for the memory system, wherein the value of the operating parameter is indicative of an operational condition associated with the memory system, and wherein the operating parameter comprises a voltage, a temperature, a status of one or more fuses, a PLL status, or a flag indicating an operability of the memory system.

12. The memory system of claim 11 , wherein the third interface comprises a pin dedicated to transmitting indications of interrupts.

13. The method of claim 1 , further comprising:
refraining from transmitting the error detection code associated with the data based at least in part on transmitting the bitwise inversion of the error detection code.

Assignees

• Micron Technology Inc

Inventors

• Balb Markus
• Hein Thomas
• Hoenigschmid Heinz

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title