Non-volatile storage device and method for accessing non-volatile storage device

Patent metadata

Field	Value
Publication number	US-2018293191-A1
Application number	US-201816009562-A
Country	US
Kind code	A1
Filing date	Jun 15, 2018
Priority date	Dec 18, 2015
Publication date	Oct 11, 2018
Grant date	—

Abstract

A non-volatile storage device is disclosed, the device includes an interface module, a control module, a read cache, and a storage chip. The interface module is configured to: receive a first read request signal sent by a host, where the first read request signal includes an address of the storage chip; when read data requested by the first read request signal is not stored in the read cache, instruct the control module to read the read data from the storage chip; and before the host ends a current read operation period, send a first interrupt signal and predetermined data to the host, where the predetermined data is used to cause the host to end the read operation period, and the first interrupt signal is used to instruct the host to execute an interrupt handler after the read operation period.

First claim

What is claimed is:

1 . A non-volatile storage device, wherein the non-volatile storage device comprises an interface module, a control module, a read cache, and a storage chip, and the interface module is configured to:
receive a first read request signal sent by a host, wherein the first read request signal comprises an address of the storage chip; when read data requested by the first read request signal is not stored in the read cache, instruct the control module to read the read data from the storage chip; and before the host ends a current read operation period, send a first interrupt signal and predetermined data to the host, wherein the predetermined data is used to cause the host to end the read operation period, and the first interrupt signal is used to instruct the host to execute an interrupt handler after the read operation period.

2 . The non-volatile storage device according to claim 1 , wherein the control module is configured to:
read the read data from the storage chip according to an instruction of the interface module, and store the read data in the read cache; and the interface module is further configured to: after the host exits the interrupt handler, receive a second read request signal sent by the host, wherein the second read request signal comprises the address of the storage chip; and send the read data stored in the read cache by the control module to the host.

3 . The non-volatile storage device according to claim 1 , wherein the non-volatile storage device further comprises a write cache, and the interface module is further configured to:
receive a first write request signal sent by the host and write data that the first write request signal requests to write, wherein the first write request signal comprises the address of the storage chip; when the write cache has no sufficient space for storing the write data, discard the write data, and instruct the control module to store data already existing in the write cache in the storage chip; and before the host ends a current write operation period, send a second interrupt signal to the host, wherein the second interrupt signal is used to instruct the host to execute the interrupt handler after the current write operation period.

4 . The non-volatile storage device according to claim 3 , wherein the control module is further configured to:
store the data already existing in the write cache in the storage chip according to an instruction of the interface module, so that the write cache reserves sufficient space to store the write data; and the interface module is further configured to: after the host exits the interrupt handler, receive a second write request signal sent by the host; and receive the write data sent by the host, and store the write data in the write cache.

5 . The non-volatile storage device according to claim 3 , wherein the first interrupt signal and/or the second interrupt signal is used to instruct the host to determine a delay time, so that the host delays in the interrupt handler according to the delay time.

6 . The non-volatile storage device according to claim 5 , wherein the interface module comprises a delay time register, and the first interrupt signal and/or the second interrupt signal is used to instruct the host to obtain the delay time from the delay time register.

7 . The non-volatile storage device according to claim 5 , wherein an inter-integrated circuit I2C bus of the non-volatile storage device connects to a general-purpose input/output GPIO chip, and the first interrupt signal and/or the second interrupt signal is used to instruct the host to determine the delay time according to the GPIO chip.

8 . The non-volatile storage device according to claim 5 , wherein the interface module comprises a first status register, the first interrupt signal and/or the second interrupt signal is used to instruct the host to determine the delay time according to the first status register, and the first status register is configured to indicate a status of the storage chip.

9 . The non-volatile storage device according to claim 5 , wherein the interface module comprises a first status register, the first status register is configured to indicate a status of the storage chip, an I2C bus of the non-volatile storage device connects to an electrically erasable programmable read-only memory EEPROM chip, the EEPROM chip is configured to indicate a correspondence between the status and the delay time, and the first interrupt signal and/or the second interrupt signal is used to instruct the host to determine the delay time according to the first status register and the EEPROM chip.

10 . The non-volatile storage device according to claim 1 , wherein the interface module comprises a second status register, and the second status register is configured to instruct the host to determine, according to the second status register, to delay in the interrupt handler.

11 . The non-volatile storage device according to claim 10 , wherein the I2C bus of the non-volatile storage device connects to a temperature sensor, and the second status register is configured to indicate that a temperature of the non-volatile storage device that is indicated by the temperature sensor does not exceed a threshold.

12 . The non-volatile storage device according to claim 10 , wherein the non-volatile storage device connects to the host by using a memory interface, and the second status register is configured to indicate that no error occurs in parity check of address and control signals of the memory interface.

13 . The non-volatile storage device according to claim 1 , wherein the storage chip comprises a flash memory chip, a phase change random access memory, or a resistive random access memory.

14 . A method for accessing a non-volatile storage device, wherein the non-volatile storage device comprises an interface module, a control module, a read cache, and a storage chip, and the method comprises:
receiving, by the interface module, a first read request signal sent by a host, wherein the first read request signal comprises an address of the storage chip; when read data requested by the first read request signal is not stored in the read cache, instructing, by the interface module, the control module to read the read data from the storage chip; and before the host ends a current read operation period, sending, by the interface module, a first interrupt signal and predetermined data to the host, wherein the predetermined data is used to cause the host to end the current read operation period, and the first interrupt signal is used to instruct the host to execute an interrupt handler after the read operation period.

15 . The method according to claim 14 , wherein the method further comprises:
reading, by the control module, the read data from the storage chip according to an instruction of the interface module, and storing the read data in the read cache; after the host exits the interrupt handler, receiving, by the interface module, a second read request signal sent by the host, wherein the second read request signal comprises the address of the storage chip; and sending, by the interface module, the read data stored in the read cache by the control module to the host.

16 . The method according to claim 14 , wherein the non-volatile storage device further comprises a write cache, and the method further comprises:
receiving, by the interface module, a first write request signal sent by the host and write data that the first write request signal requests to write, wherein the first write request

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Yansong

Classifications

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0611

  in relation to response time · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F13/161

  with latency improvement · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title