Non-volatile memory integrated with artificial intelligence system for preemptive block management

Patent metadata

Field	Value
Publication number	US-12099743-B2
Application number	US-202217709745-A
Country	US
Kind code	B2
Filing date	Mar 31, 2022
Priority date	Mar 31, 2022
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current operation of the non-volatile storage apparatus to make a second level prediction about defects. In one embodiment, the first level prediction is faster to make and uses less data collection, but is not as reliable, as the second level prediction. While second level prediction is more reliable, it takes more time to perform and requires a more intensive data collection, so it is only used when needed.

First claim

What is claimed is:

1. A non-volatile storage apparatus, comprising:
non-volatile memory cells configured to store host data in addition to a first pre-trained artificial intelligence (“AI”) model and a second pre-trained AI model, the second pre-trained AI model is different than the first pre-trained AI model;
one or more control circuits connected to the non-volatile memory cells; and
an inference circuit connected to the one or more control circuits;
the inference circuit is configured to use the first pre-trained AI model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus in order to make a first level prediction as to whether a defect exists in groupings of the non-volatile memory cells;
the one or more control circuits are configured to categorize as potentially defective groupings of the non-volatile memory cells for which the first level prediction concluded that a defects exists;
the inference circuit is configured to, in response to more than a threshold number of groupings of the non-volatile memory cells being categorized as potentially defective, use the second pre-trained AI model with a second set of one or more metrics describing current operation of the non-volatile storage apparatus in order to make a second level prediction as to whether a defect exists in one or more groupings of the non-volatile memory cells that are categorized as potentially defective; and
the one or more control circuits are configured to categorize groupings of the non-volatile memory cells as actually defective and prevent further use with host data for groupings of the non-volatile memory cells that the second level prediction concluded a defect exists.

2. The non-volatile storage apparatus of claim 1 , wherein:
the first pre-trained AI model is received pre-trained from a source external to the non-volatile storage apparatus; and
the second pre-trained AI model is received pre-trained from a source external to the non-volatile storage apparatus.

3. The non-volatile storage apparatus of claim 1 , wherein:
the groupings of the non-volatile memory cells are blocks of non-volatile memory cells;
a first set of the blocks are configured to store host data;
a second set of the blocks are configured to store the first model; and
a third set of the blocks are configured to store the second model.

4. The non-volatile storage apparatus of claim 1 , wherein:
the groupings of the non-volatile memory cells are blocks of non-volatile memory cells;
the one or more one or more control circuits are configured to categorize as potentially defective by adding to a potential bad block pool those groupings of the non-volatile memory cells for which the first level prediction concluded that a defects exists; and
the one or more one or more control circuits are configured to categorize groupings of the non-volatile memory cells as actually defective and prevent further use with host data by adding to the actual bad block pool those groupings of the non-volatile memory cells that the second level prediction concluded a defect exists.

5. The non-volatile storage apparatus of claim 1 , wherein:
the one or more control circuits are configured to perform gathering of the first set of one or more metrics describing current operation of the non-volatile storage system at a first time;
the one or more control circuits are configured to perform gathering of the second set of one or more metrics describing current operation of the non-volatile storage system at a second time that is after the first time; and
the time duration for gathering the second set of one or more metrics is longer than the time duration for gathering the first set of one or more metrics.

6. The non-volatile storage apparatus of claim 1 , wherein the one or more control circuits are configured to:
categorize as potentially defective those groupings of the non-volatile memory cells for which the first level prediction concluded with low confidence that a defects exists; and
categorize as actually defective those groupings of the non-volatile memory cells for which the first level prediction concluded with high confidence that a defects exists.

7. The non-volatile storage apparatus of claim 1 , wherein:
the first pre-trained AI model is used to predict defect or no defect;
the second pre-trained AI model is used to predict defect or no defect;
the second pre-trained AI model is used to predict a type of defect;
the first pre-trained AI model is not used to predict a type of defect; and
the second pre-trained AI model requires more metrics than the first model.

8. The non-volatile storage apparatus of claim 1 , wherein:
the second set of one or more metrics includes more data than the first set of one or more metrics.

9. The non-volatile storage apparatus of claim 1 , wherein:
the second level prediction includes an indication of a type of defect;
the first level prediction does not include an indication of the type of defect; and
the second level prediction is more time intensive than the first level prediction.

10. The non-volatile storage apparatus of claim 1 , wherein:
the non-volatile memory cells are arranged on multiple memory die assemblies arranged in a stack of memory die assemblies;
the one or more control circuits include a controller on a separate die from the multiple memory die assemblies and positioned underneath the stack of memory die assemblies; and
the inference circuit is on a separate die from the multiple memory die assemblies and the controller, the inference circuit is positioned underneath the stack of memory die assemblies.

11. The non-volatile storage apparatus of claim 1 , wherein:
the non-volatile memory cells are arranged on multiple memory die assemblies arranged in a stack of memory die assemblies;
the one or more control circuits include a controller on a controller die that is a separate die from the multiple memory die assemblies and positioned underneath the stack of memory die assemblies; and
the inference circuit is positioned on the controller die.

12. The non-volatile storage apparatus of claim 1 , wherein:
the non-volatile memory cells are arranged on a memory die;
the one or more control circuits include a control die directly bonded to the memory die; and
the inference circuit is on a third die that is directly bonded to the memory die.

13. The non-volatile storage apparatus of claim 12 , wherein:
an electrical path that runs from the control die to the memory die to the third die;
the third die includes a first set of bond pads;
the memory die has a second set of bond pads directly connected to the first set of bond pads on the third die and third set of bond pads;
the second set of bond pads are on a first surface of the memory die and the third set of bond pads are on a second surface of the memory die that is opposite the first surface; and
the control die includes a fourth set of bond pads directly connected to the third set of bond pads on the memory die.

14. The non-volatile storage apparatus of claim 13 , wherein:
the third die includes a chip pad;
the third die includes a through silicon via (TSV) connecting a bond pad of the first set of bond pads to the chip pad; and
the TSV is in electrical communication with the control die via the memory die.

15. The non-volatile storage apparatus of claim 1 , wherein the non-volatile memory cells comprise:
a stack of alternating dielectric layers and conductive layers,
vertical columns implemented in the stack, a first subset of the vertical columns form vertic

Assignees

• Western Digital Tech Inc
• Sandisk Technologies Inc

Inventors

• Li Liang
• Tu Loc
• Yu Yinfeng
• Tian Xuan

Classifications

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06N5/04

  Inference or reasoning models · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title