Gate driver

Patent metadata

Field	Value
Publication number	US-12095451-B2
Application number	US-202217653730-A
Country	US
Kind code	B2
Filing date	Mar 7, 2022
Priority date	Oct 8, 2021
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

A gate driver to control a high-power switching device is disclosed. The gate driver includes a multifunction pin that allows the gate driver to be controlled by a multifunction signal to perform a number of different functions. For example, a level of the multifunction signal at the multifunction pin can enable/disable the output of the gate driver. In another example, a level of the multifunction signal that is held for a period while the gate driver is in a fault state can reset the state of the gate driver. In another example, pulsing the multifunction signal a number of times can activate a test of the fault detection capabilities of the gate driver. Utilizing one pin for this control, simplifies circuit complexity for communication between a controller and the gate driver, thereby reducing cost and increasing reliability.

First claim

The invention claimed is:

1. A high-power switching system comprising:
a switching device;
a gate driver having an input pin, a fault pin, and a multifunction pin for a multifunctional signal; and
a controller configured to:
transmit an input signal to the input pin of the gate driver to control operation of the switching device,
receive a fault signal from the fault pin of the gate driver to monitor a fault in the switching device, and
transmit a multifunction signal to the multifunction pin of the gate driver to control operation of the gate driver; wherein the gate driver is configured by the multifunction signal to:
disable an output pin of the gate driver when the multifunction signal is in a first binary state;
activate a fault test to test a fault detector circuit of the gate driver when the multifunction signal is pulsed between the first binary state and a second binary state for a number of consecutive pulses; and
clear the fault signal of the fault detected by the fault detector circuit of the gate driver when the multifunction signal is held in the first binary state for a period greater than a threshold to clear the fault signal.

2. The high-power switching system according to claim 1 , wherein the fault is a short circuit in the switching device or an over-current in the switching device.

3. The high-power switching system according to claim 1 , wherein the fault test is a desaturation (DESAT) test or a CS test.

4. The high-power switching system according to claim 1 , wherein the switching device is an IGBT.

5. The high-power switching system according to claim 1 , wherein the switching device is a power MOSFET.

6. The high-power switching system according to claim 1 , wherein the fault test configures the gate driver to generate the fault signal at a level corresponding to the fault, the level corresponding to the fault held until cleared by the multifunction signal.

7. The high-power switching system according to claim 1 , wherein the first binary state is LOW and wherein when the multifunction signal is made LOW, the gate driver is configured in a disabled state that includes the output pin being LOW and the fault pin indicating no fault.

8. The high-power switching system according to claim 1 , wherein when the multifunction signal is pulsed between the first binary state and the second binary state for the number of consecutive pulses, the gate driver is configured in a desaturation (DESAT) test state that includes holding a desaturation-check (DSCHK) signal HIGH to enable circuitry to generate a DESAT signal to cause the fault.

9. The high-power switching system according to claim 1 , wherein the gate driver includes isolation to separate a low-power side from a high-power side.

10. The high-power switching system according to claim 1 wherein the gate driver includes:
a driver circuit configured to receive the input signal at the input pin of the gate driver and to transmit an output signal to the switching device coupled at a gate terminal to the output pin of the gate driver; and
a fault communication circuit coupled to the fault detector circuit and configured to set the fault signal when the fault is detected and transmit the fault signal to the fault pin of the gate driver.

11. The high-power switching system according to claim 10 , wherein the driver circuit is configured to transmit a LOW output signal when the multifunction signal is LOW.

12. The high-power switching system according to claim 11 , wherein the driver circuit is configured to transmit the output signal as a replica of the input signal when the multifunction signal is HIGH.

13. The high-power switching system according to claim 10 , wherein the fault communication circuit includes a latch that is set to a fault level by the fault detector circuit in response to the fault.

14. The high-power switching system according to claim 13 , wherein the latch is reset to a normal level when the multifunction signal is held LOW for the period greater than the threshold.

15. The high-power switching system according to claim 10 , wherein the fault detector circuit includes:
a shift register coupled to the multifunction pin, the shift register outputting a DSCHK signal to activate the fault test of the fault detector circuit after receiving a number of consecutive pulses in the multifunction signal.

16. The high-power switching system according to claim 10 , wherein the fault detector circuit configured to receive a desaturation signal at a desaturation (DESAT) pin of the gate driver, the fault detector circuit including:
a capacitor that is coupled externally to the gate driver at the DESAT pin;
a discharge transistor configured to discharge the capacitor to ground when turned ON; and
a current source configured to charge the capacitor when the discharge transistor is turned OFF, a voltage on the capacitor being the desaturation signal at the DESAT pin.

17. The high-power switching system according to claim 16 , wherein the fault test of the fault detector circuit includes configuring the fault detector circuit to:
charge the capacitor to increase the voltage at the DESAT pin;
compare the voltage at the DESAT pin to a threshold; and
detect the fault when the voltage exceeds the threshold.

18. A high-power switching system comprising:
a controller;
a switching device; and
a gate driver including:
a driver circuit configured to receive an input signal at an input pin of the gate driver and to transmit an output signal to a switching device coupled at a gate terminal to an output pin of the gate driver;
a fault detector circuit configured to receive a desaturation signal at a desaturation (DESAT) pin of the gate driver to detect a fault in the switching device;
a fault communication circuit coupled to the fault detector circuit and configured to set a fault signal when a fault is detected and transmit the fault signal to a fault pin of the gate driver; and
a multifunction pin configured to receive a multifunction signal, the gate driver configured by the multifunction signal to:
enable the driver circuit when the multifunction signal is in a first binary state or disable the driver circuit when the multifunction signal is in a second binary state;
activate a test of the fault detector circuit when the multifunction signal is pulsed between the first binary state and the second binary state for a number of consecutive pulses; and
reset the fault communication circuit when the multifunction signal is held in the second binary state for a period greater than a threshold.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Song Kinam
• Kuban Michal
• Anghel Vlad
• Rahamim Guy
• Constantino John

Classifications

• H03K17/08128

  in composite switches · CPC title

• H02H3/08

  responsive to excess current (responsive to abnormal temperature caused by excess current H02H5/04) · CPC title

• H02H3/06

  with automatic reconnection · CPC title

• G01R31/3277

  of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches · CPC title

• H03K17/0828

  in composite switches · CPC title