Electrostatic discharge guard ring with complementary drain extended devices

Patent metadata

Field	Value
Publication number	US-12094970-B2
Application number	US-202117174023-A
Country	US
Kind code	B2
Filing date	Feb 11, 2021
Priority date	Oct 23, 2017
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a p-channel device and an n-channel device. The p-channel device includes an n-type barrier region circumscribing a p-type drain region with an n-type body region. The p-channel device may be positioned adjacent to the n-channel device and a high voltage junction diode.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a p-type substrate having a first circuit region and a second circuit region;
an n-doped barrier structure segregating the first circuit region from the second circuit region, the n-doped barrier structure having a notch with an opening facing away from the first circuit region; and
a p-type drain-extended metal oxide semiconductor (P-DEMOS) transistor positioned partially within the notch, the P-DEMOS transistor including:
a p-doped drain region extending along a length dimension between a first end and a second end, and extending along a width dimension between a first side and a second side;
an n-doped body region circumscribing the p-doped drain region along the first and second ends and the first and second sides; and
a p-doped source contact separated from the p-doped drain region by the n-doped body region near the second end.

2. The integrated circuit of claim 1 , in which the P-DEMOS transistor is positioned completely within the notch.

3. The integrated circuit of claim 1 , in which the p-doped drain region includes:
a highly doped region near the first end, and having a first dopant concentration and first length along the length dimension; and
a lightly doped region between the highly doped region and the n-doped body region, and having a second dopant concentration and second length along the length dimension, the second dopant concentration lower than the first dopant concentration, and the second length greater than the first length.

4. The integrated circuit of claim 1 , in which the n-doped barrier structure includes a contiguous ring structure circumscribing the first circuit region.

5. The integrated circuit of claim 1 in which the first circuit region is a high voltage region.

6. The integrated circuit of claim 1 in which the n-doped barrier structure is a contiguous ring structure circumscribing the first circuit region.

7. The integrated circuit of claim 1 in which the n-doped barrier structure is a segmented ring structure circumscribing the first circuit region.

8. The integrated circuit of claim 1 in which the n-doped barrier structure isolates high voltage operations in the first circuit region from reaching the second circuit region.

9. The integrated circuit of claim 1 including a segmented electrostatic guard ring surrounding the first circuit region that includes the n-doped barrier structure.

10. The integrated circuit of claim 1 including a segmented electrostatic guard ring surrounding the first circuit region that includes the P-DEMOS transistor and a diode segment.

11. The integrated circuit of claim 1 including a segmented electrostatic guard ring surrounding the first circuit region that includes the P-DEMOS transistor and a lateral drain metal oxide semiconductor (LDMOS) transistor segment.

12. The integrated circuit of claim 1 including a segmented electrostatic guard ring surrounding the first circuit region that includes the P-DEMOS transistor, a diode segment, and a lateral drain metal oxide semiconductor (LDMOS) transistor segment.

13. The integrated circuit of claim 1 in which the second circuit region is a low voltage region.

14. An integrated circuit, comprising:
a p-doped substrate having a first circuit region and a second circuit region;
an n-doped barrier structure between the first circuit region and the second circuit region, the n-doped barrier structure including first and second colinear segments both having a side toward the second circuit region, a first notch segment extending from the first colinear segment toward the first circuit region, a second notch segment extending from the second colinear segment toward the first circuit region, and a third notch segment that connects the first and second notch segments; and
a p-doped drain-extended metal oxide semiconductor (P-DEMOS) transistor, including:
a p-doped drain region bounded horizontally by an n-doped body region an n-doped body region; and
a p-doped source contact spaced apart from the p-doped drain region by the n-doped body region,

wherein the n-doped body region extends toward the second circuit region past the sides of the first and second colinear segments.

15. The integrated circuit of claim 14 , in which the n-doped barrier structure includes a contiguous ring structure circumscribing the first circuit region.

16. The integrated circuit of claim 14 in which the first circuit region is a high voltage region.

17. The integrated circuit of claim 14 in which the n-doped barrier structure is a segmented ring structure circumscribing the first circuit region.

18. The integrated circuit of claim 14 in which the n-doped barrier structure isolates high voltage operations in the first circuit region from low voltage operations in the second circuit region.

19. An integrated circuit, comprising:
a semiconductor substrate having a high-voltage circuit region and a low-voltage circuit region;
an n-type barrier structure between the high-voltage circuit region and the low-voltage circuit region, the n-type barrier structure including first and second colinear segments and a third segment parallel to and spaced apart from the colinear segments toward the high-voltage circuit region; and
a p-type drain-extended metal oxide semiconductor (P-DEMOS) transistor, including:
a p-type drain region surrounded horizontally by an n-type body region and an n-type barrier region; and
a p-type source contact spaced apart from the p-type drain region by the n-type body region,

wherein the n-type barrier region extends between the first and second colinear segments.

20. The integrated circuit of claim 19 in which the high-voltage circuit region is configured to operate up to about 700V, and the low-voltage circuit region is configured to operate at 15V or less.

Assignees

• Texas Instruments Inc

Inventors

• Kim Sunglyong
• Sridhar Seetharaman
• Pendharkar Sameer
• LaFonteese David

Classifications

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D64/112

  comprising multiple field plate segments · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/371

  Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current · CPC title