Heterostructure of an electronic circuit having a semiconductor device

US12094964B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12094964-B2
Application numberUS-202318332119-A
CountryUS
Kind codeB2
Filing dateJun 9, 2023
Priority dateJul 12, 2018
Publication dateSep 17, 2024
Grant dateSep 17, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a semiconductor device is provided that includes a III-V heterostructure, the III-V heterostructure including a first layer including GaN to which a second layer adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), and having a purity such that the 2-dimensional electron gas is not present. It is therefore advantageous for the present electronic circuit to be enclosed such that, in operation, no light of wavelengths of less than 400 nm may reach the III-V heterostructure and free charge carriers may be generated by these wavelengths.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic circuit having a semiconductor device that comprises: a heterostructure including a first layer and a second layer that together form a channel, wherein: the first layer comprises a compound semiconductor to which the second layer adjoins, the heterostructure is a III-V heterostructure, the first layer includes fewer than 1×10 17 cm −3 unintentional background impurities, and the heterostructure is grown on a substrate with a dislocation defect density of less than 1×10 7 cm −2 . 2. The electronic circuit according to claim 1 , wherein the heterostructure includes GaN. 3. The electronic circuit according to claim 1 , wherein the substrate includes GaN. 4. The electronic circuit according to claim 1 , wherein the semiconductor device includes a buffer layer which adjoins to the heterostructure. 5. The electronic circuit according to claim 1 , wherein the first layer has a thickness less than 100 nm. 6. The electronic circuit according to claim 1 , wherein the first layer has a dislocation defect density of less than 1×10 7 cm 2 . 7. The electronic circuit according to claim 1 , such that a 2-dimensional electron gas is formed in the channel when an electrical potential is applied. 8. The electronic circuit according to claim 1 , wherein the channel, in the absence of an external field, is substantially free of electrons from a 2-dimensional electron gas such that the entire channel is non-conducting. 9. An electronic circuit having a semiconductor device that comprises: a heterostructure including a first layer and a second layer that together form a channel, wherein: the first layer comprises a compound semiconductor to which the second layer adjoins, the heterostructure is a III-V heterostructure, the first layer includes fewer than 1×10 17 cm −3 oxygen atoms, and the heterostructure is grown on a substrate with a dislocation defect density of less than 1×10 7 cm −2 . 10. The electronic circuit according to claim 9 , wherein the heterostructure includes GaN. 11. The electronic circuit according to claim 9 , wherein the substrate includes GaN. 12. The electronic circuit according to claim 9 , wherein the semiconductor device includes a buffer layer which adjoins to the heterostructure. 13. The electronic circuit according to claim 9 , wherein the first layer has a thickness less than 100 nm. 14. The electronic circuit according to claim 9 , wherein the first layer has a dislocation defect density of less than 1×10 7 cm −2 . 15. The electronic circuit according to claim 9 , such that a 2-dimensional electron gas is formed in the channel when an electrical potential is applied. 16. The electronic circuit according to claim 9 , wherein the channel, in the absence of an external field, is substantially free of electrons from a 2-dimensional electron gas such that the entire channel is non-conducting.

Assignees

Inventors

Classifications

  • Nitride Group III-V materials, e.g. AlN or GaN · CPC title

  • comprising only Group II-VI materials heterojunctions, e.g. CdTe/HgTe heterojunctions · CPC title

  • comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

  • being Group II-VI materials, e.g. ZnO · CPC title

  • Vertical HEMTs or vertical HHMTs · CPC title

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What does patent US12094964B2 cover?
An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a se…
Who is the assignee on this patent?
Namlab Ggmbh, Univ Dresden Tech
What technology area does this patent fall under?
Primary CPC classification H10D62/8503. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 17 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).