Semiconductor structure having deep metal line and method for forming the semiconductor structure

Patent metadata

Field	Value
Publication number	US-12094816-B2
Application number	US-202117460859-A
Country	US
Kind code	B2
Filing date	Aug 30, 2021
Priority date	Aug 30, 2021
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

A semiconductor structure includes a substrate, a dielectric layer, a first conductive feature and a second conductive feature. The substrate includes a semiconductor device. The dielectric layer is disposed on the substrate. The first conductive feature is formed in the first dielectric layer. The second conductive feature penetrates the first conductive feature and the dielectric layer, and is electrically connected to the first conductive feature and the semiconductor device.

First claim

What is claimed is:

1. A method for making a semiconductor structure, comprising:
forming a dielectric layer to cover a transistor;
forming a first conductive feature in the dielectric layer, the first conductive feature being electrically isolated from the transistor;
after forming the first conductive feature, forming a through hole that penetrates the first conductive feature and the dielectric layer to expose a contact of the transistor; and
forming a second conductive feature in the through hole so as to permit the first conductive feature to be electrically connected to the contact of the transistor through the second conductive feature.

2. The method as claimed in claim 1 , wherein the first conductive feature and the second conductive feature are made of different materials, each of the first conductive feature and the second conductive feature having a top surface that faces away from the transistor, and a bottom surface that confronts the transistor, the top surface of the first conductive feature being flush with the top surface of the second conductive feature.

3. The method as claimed in claim 1 , wherein:
the first conductive feature is made of a material including copper, ruthenium, tungsten, titanium, aluminum, cobalt, molybdenum, iridium, rhodium, cobalt-tungsten-phosphorus or combinations thereof; and
the second conductive feature is made of a material including copper, ruthenium, tungsten, titanium, aluminum, cobalt, molybdenum, iridium, rhodium, cobalt-tungsten-phosphorus or combinations thereof.

4. The method as claimed in claim 1 , wherein:
the through hole is defined by a hole-defining wall;
the method further comprises:
after the formation of the through hole and before the formation of the second conductive feature, conformally forming an electrically conductive barrier layer on the hole-defining wall, and conformally forming an electrically conductive liner layer on the electrically conductive barrier layer; and
after the formation of the second conductive feature, the second conductive feature is surrounded by and connected to the electrically conductive liner layer.

5. The method as claimed in claim 1 , wherein forming the through hole is conducted by using a photoresist as a mask to etch through the first conductive feature and the dielectric layer.

6. The method as claimed in claim 1 , wherein, in forming the through hole, the through hole is defined by a hole-defining wall that forms an included angle with the transistor, the included angle ranging from 72 degrees to 90 degrees, such that the second conductive feature in the through hole has an outer wall that forms another included angle with the transistor, the another included angle between the outer wall and the transistor ranging from 72 degrees to 90 degrees.

7. The method as claimed in claim 1 , wherein, in forming the through hole, the contact of the transistor is partially removed.

8. A method for making a semiconductor structure, comprising:
forming a dielectric layer to cover a transistor;
forming a first conductive feature on the dielectric layer opposite to the transistor, the first conductive feature being electrically isolated from the transistor; and
after forming the first conductive feature, forming a second conductive feature that penetrates the first conductive feature and the dielectric layer so as to permit the first conductive feature to be electrically connected to the transistor through the second conductive feature.

9. The method as claimed in claim 8 , wherein the first conductive feature and the second conductive feature are made of different materials.

10. The method as claimed in claim 8 , wherein
the first conductive feature includes copper, ruthenium, tungsten, titanium, aluminum, cobalt, molybdenum, iridium, rhodium, graphene, or combinations thereof, and
the second conductive feature includes copper, ruthenium, tungsten, titanium, aluminum, cobalt, molybdenum, iridium, rhodium, cobalt-tungsten-phosphorus, or combinations thereof.

11. The method as claimed in claim 8 , further comprising:
forming a barrier layer to surround the second conductive feature; and
forming a liner layer between the barrier layer and the second conductive feature.

12. The method as claimed in claim 11 , wherein each of the barrier layer and the liner layer is made of a conductive material including tantalum, tantalum nitride, cobalt, ruthenium, titanium, titanium nitride, manganese nitride, or combinations thereof.

13. The method as claimed in claim 8 , wherein the second conductive feature has an outer wall that forms an included angle with a top surface of a contact of the transistor, the included angle ranging from 72 degrees to 90 degrees.

14. The method as claimed in claim 8 , wherein the transistor includes a source region, a drain region and a contact formed on one of the source region and the drain region, the second conductive feature being formed to permit electrical connection with the contact of the transistor.

15. A method for making a semiconductor structure, comprising:
forming a first dielectric layer on at least one transistor that is partly formed in a substrate;
forming an interconnect structure that includes
a second dielectric layer formed on the first dielectric layer, and
a first conductive feature formed in the second dielectric layer, the first conductive feature being electrically isolated from the at least one transistor; and

after forming the interconnect structure, forming a second conductive feature in a way that the second conductive feature penetrates the interconnect structure and the first dielectric layer to permit the first conductive feature to be electrically connected to the at least one transistor through the second conductive feature.

16. The method as claimed in claim 15 , further comprising:
forming a glue layer between the first dielectric layer and the first conductive feature;
forming a barrier layer to surround the second conductive feature in a way that the barrier layer is formed to separate the second conductive feature from the interconnect structure, the first dielectric layer and the at least one transistor; and
forming a liner layer between the barrier layer and the second conductive feature.

17. The method as claimed in claim 15 , wherein
the first conductive feature includes multiple conductive components that are spaced apart from each other through the second dielectric layer, and
the second conductive feature is formed to penetrate the first dielectric layer and at least one of the multiple conductive components so as to permit the at least one of the multiple conductive components to be electrically connected to the at least one transistor through the second conductive feature.

18. The method as claimed in claim 15 , wherein
the at least one transistor includes a contact,
the second conductive feature has a bottom surface that is disposed on the contact of the at least one transistor, and
the first conductive feature has a top surface facing away from the at least one transistor, and a bottom surface that confronts the at least one transistor and that is disposed on the first dielectric layer, the bottom surface of the first conductive feature being at a higher level than the bottom surface of the second conductive feature.

19. The method as claimed in claim 18 , wherein the second conductive feature is partially landed on the contact of the at least one transistor.

20. The method as claimed in claim 15 , wherein
the at least

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chu Wei-Chen
• Wu Chia-Tien
• Su Chia-Wei
• Liao Yu-Chieh
• Lee Chia-Chen
• Chen Hsin-Ping
• Shue Shau-Lin

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/48

  Insulating materials thereof · CPC title