Stacked transistor chip package with source coupling

Patent metadata

Field	Value
Publication number	US-12094807-B2
Application number	US-202117485742-A
Country	US
Kind code	B2
Filing date	Sep 27, 2021
Priority date	Oct 16, 2020
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.

First claim

What is claimed is:

1. A package, which comprises:
a first transistor chip having a first source pad;
a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area, where the interface area is an area where the first transistor chip faces the second transistor chip,
wherein the first source pad and the second source pad are coupled at the interface area, and wherein the first transistor chip is mounted on a carrier;
wherein a first gate pad of the first transistor chip and a second gate pad of the second transistor chip are arranged at the interface area;
an electrically conductive first clip arranged at least partially in the interface area between the first transistor chip and the second transistor chip, wherein the first clip is coupled to a first side of the carrier; and
an electrically conductive second clip mounted on a top side of the second transistor chip and coupled to a second side of the carrier, wherein the second side is adjacent to the first side.

2. The package according to claim 1 , comprising:
the first gate pad is coupled with the second gate pad; or
the first gate pad and the second gate pad are configured to be separately controllable.

3. The package according to claim 1 , wherein the first transistor chip has a first drain pad at a main surface of the first transistor chip facing away from the interface area, and/or the second transistor chip has a second drain pad at a main surface of the second transistor chip facing away from the interface area.

4. The package according to claim 3 , wherein the electrically conductive second clip couples the second drain pad with the second side of the carrier.

5. The package according to claim 1 , wherein the first transistor chip and the second transistor chip are connected to function as a single common transistor.

6. The package according to claim 1 , comprising:
the first transistor chip and the second transistor chip have different shapes and/or dimensions.

7. The package according to claim 1 , wherein the carrier comprises a leadframe.

8. The package according to claim 1 , wherein the electrically conductive first clip has a second coupling section coupling the first gate pad and/or the second gate pad with a third side of the carrier that is opposite to the first side of the carrier.

9. The package according to claim 1 , wherein the electrically conductive first clip has a first coupling section coupling the first source pad and the second source pad with the first side of the carrier.

10. The package according to claim 1 , comprising an encapsulant, in particular a mold compound, encapsulating at least part of the first transistor chip and at least part of the second transistor chip.

11. The package according to claim 1 , comprising a third transistor chip and a fourth transistor chip stacked on the third transistor chip, wherein the third transistor chip and the fourth transistor chip are arranged laterally to the first transistor chip and the second transistor chip.

12. A package, comprising:
a first transistor chip having a first source pad, a first gate pad and a first drain pad;
a second transistor chip having a second source pad, a second gate pad and a second drain pad, wherein the second transistor chip is stacked with the first transistor chip at an interface area;
a first laminate that is a first printed circuit board in which the first transistor chip is embedded, wherein the first laminate includes a first metal structured layer connected to the first source pad, the first gate pad and the first drain pad of the first transistor chip;
a second laminate that is a second printed circuit board in which the second transistor chip is embedded, wherein the second laminate includes a second metal structured layer connected to the second source pad, the second gate pad and the second drain pad of the second transistor chip; and
a connection structure, in particular a solder structure, arranged in the interface area between the first metal structured layer of the first laminate and the second metal structured layer of the second laminate and configured for coupling the first source pad with the second source pad, the first gate pad with the second gate pad, and the first drain pad with the second drain pad of the respective first transistor chip and the second transistor chip.

13. The package according to claim 12 , comprising a metallic structure for coupling the first transistor chip with the second transistor chip.

14. The package according to claim 13 , wherein the metallic structure comprises at least one of the group consisting of at least one continuous metal layer, at least one patterned metal layer, at least one vertical metal element, and at least one electrically conductive clip.

15. The package according to claim 13 , wherein part of the metallic structure connects a top side of the second transistor chip with a bottom side of the package and partially extends to laterally enclose the first transistor chip and the second transistor chip.

16. A package, comprising:
a first transistor chip having a first source pad, a first gate pad and a first drain pad;
a second transistor chip having a second source pad, a second gate pad and a second drain pad, wherein the second transistor chip is stacked with the first transistor chip at an interface area between the first transistor chip and the second transistor chip;
a laminate that is a printed circuit board in which the first transistor chip is embedded, wherein the laminate includes a metal structured layer connected to the first source pad, the first gate pad and the first drain pad of the first transistor chip;
an encapsulant in which the second transistor chip is encapsulated; and
a connection structure, in particular a leadframe and a clip, the leadframe arranged in the interface area between the metal structured layer of the laminate and the encapsulant, the leadframe and the clip configured for coupling the first source pad with the second source pad, the first gate pad with the second gate pad, and the first drain pad with the second drain pad of the respective first transistor chip and the second transistor chip.

Assignees

• Infineon Technologies Ag

Inventors

• Yuferev Sergey
• Calo Paul Armand Asentista
• Long Theng Chao
• Maerz Josef
• Ng Chee Yang
• Palm Petteri
• Yong Wae Chet

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W70/481 Primary

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/466

  Tape carriers or flat leads · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title