Look-up table read

Patent metadata

Field	Value
Publication number	US-12093690-B2
Application number	US-202217952517-A
Country	US
Kind code	B2
Filing date	Sep 26, 2022
Priority date	May 27, 2019
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.

First claim

What is claimed is:

1. A device comprising:
a memory configured to store a set of tables;
an intermediate register coupled to the memory;
a butterfly network coupled to the intermediate register;
a destination register coupled to the intermediate register;
a processor functional unit coupled to the memory; and
a decoder coupled to the processor functional unit and configured to:
receive an instruction that specifies a set of indices and the destination register;
based on the instruction, cause the processor functional unit to:
read a set of table elements from the set of tables by, for each table of the set of tables, reading a respective subset of the set of table elements based on a respective index of the set of indices; and
store the set of table elements in the intermediate register in a first order; and

based on the instruction, cause the butterfly network to:
reorder the set of table elements to be in a second order; and
store the set of table elements in the destination register in the second order.

2. The device of claim 1 , wherein:
the memory includes a set of banks; and
the first order is based on an arrangement of the set of table elements among the set of banks of the memory.

3. The device of claim 1 , wherein:
the set of tables includes a set of columns; and
the first order is based on an arrangement of the set of table elements among the set of columns.

4. The device of claim 1 , wherein the memory is a level one (L1) cache.

5. The device of claim 1 , wherein:
the instruction further specifies a number of table elements to read in addition to an indexed table element; and
the processor functional unit is configured to:
read a first table element from the set of tables based on the set of indices; and
determine whether to read a second table element from the set of tables based on the number of table elements to read in addition to the indexed table element.

6. The device of claim 1 , wherein the instruction further specifies whether to perform extension on the set of table elements prior to storing in the destination register.

7. The device of claim 1 , wherein the instruction specifies the set of indices by specifying a vector source index register that stores the set of indices.

8. The device of claim 1 further comprising a base address register configured to store a base address of the set of tables, wherein the instruction specifies the set of tables by specifying the base address register.

9. The device of claim 1 further comprising a configuration register configured to store a configuration of the set of tables, wherein the instruction specifies the configuration register.

10. The device of claim 9 , wherein the configuration specifies a size of each of the set of data elements.

11. The device of claim 9 , wherein the configuration specifies a size of each table of the set of tables.

12. The device of claim 9 , wherein the configuration specifies a number of tables in the set of tables.

13. A processor comprising:
a level one (L1) cache that includes a first portion configured as a data cache and a second portion configured to be directly accessible, wherein the second portion is configured to store a set of tables;
an intermediate register coupled to the L1 cache;
a butterfly network coupled to the intermediate register;
a destination register coupled to the L1 cache; and
a functional unit coupled to the L1 cache and configured to, based on an instruction:
read a set of table elements from the set of tables based on a set of indices;
store the set of table elements in the intermediate register in a first order;
cause the butterfly network to reorder the set of table elements to be in a second order; and
store the set of table elements in the destination register in the second order.

14. The processor of claim 13 , wherein:
the L1 cache includes a set of banks; and
the first order is based on an arrangement of the set of table elements among the set of banks of the L1 cache.

15. The processor of claim 13 , wherein:
the set of tables includes a set of columns; and
the first order is based on an arrangement of the set of table elements among the set of columns.

16. A method comprising:
storing a set of tables in a memory;
receiving an instruction that specifies a set of indices and a destination register; and
executing the instruction by a functional unit, including:
reading a set of table elements from the set of tables based on the set of indices;
storing the set of table elements in an intermediate register in a first order;
reordering the set of table elements to be in a second order using a butterfly network; and
storing the set of table elements in the destination register in the second order.

17. The method of claim 16 , wherein:
the memory includes a set of banks; and
the first order is based on an arrangement of the set of table elements among the set of banks of the memory.

18. The method of claim 16 , wherein:
the set of tables includes a set of columns; and
the first order is based on an arrangement of the set of table elements among the set of columns.

19. The method of claim 16 , wherein the memory is a level one (L1) cache.

20. The method of claim 16 , wherein:
the instruction further specifies a number of table elements to read in addition to an indexed table element; and
the method further comprises:
reading a first table element from the set of tables based on the set of indices; and
determining whether to read a second table element from the set of tables based on the number of table elements to read in addition to the indexed table element.

Assignees

• Texas Instruments Inc

Inventors

• Bhoria Naveen
• Samudrala Dheera Balasubramanian
• Bui Duc
• Davis Alan

Classifications

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/355

  Indexed addressing · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30007

  to perform operations on data operands · CPC title

• G06F2212/1056

  Simplification · CPC title