Photonic communication platform

US12092866B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12092866-B2
Application numberUS-202318455395-A
CountryUS
Kind codeB2
Filing dateAug 24, 2023
Priority dateMar 6, 2019
Publication dateSep 17, 2024
Grant dateSep 17, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for fabricating a photonic system, comprising: using a stepper machine to lithographically pattern a semiconductor wafer with a plurality of photonic modules, wherein patterning the semiconductor wafer comprises: patterning the semiconductor wafer with a first photonic module using at least a first photomask; and subsequent to patterning the semiconductor wafer with the first photonic module, patterning the semiconductor wafer with a second photonic module using at least the first photomask; wherein each of the first and second photonic modules, when patterned, comprises: first and second boundaries; an optical distribution network; a first optical waveguide optically coupling the optical distribution network to a first neighboring photonic module of the plurality of photonic modules, the first neighboring photonic module being adjacent to the first boundary; and a second optical waveguide optically coupling the optical distribution network to a second neighboring photonic module of the plurality of photonic modules, the second neighboring photonic module being adjacent to the second boundary. 2. The method of claim 1 , wherein the first and second boundaries are opposite to one another. 3. The method of claim 1 , wherein patterning the semiconductor wafer with the first photonic module using at least the first photomask comprises patterning the semiconductor wafer with the first and second optical waveguides of the first photonic module using the first photomask. 4. The method of claim 3 , wherein patterning the semiconductor wafer with the second photonic module using at least the first photomask comprises patterning the semiconductor wafer with the first and second optical waveguides of the second photonic module using the first photomask. 5. The method of claim 1 , wherein: patterning the semiconductor wafer with the first photonic module is performed using at least a plurality of photomasks including the first photomask, and patterning the semiconductor wafer with the second photonic module is performed using at least the plurality of photomasks. 6. The method of claim 5 , wherein: patterning the semiconductor wafer with the first photonic module comprises forming a first doped region using a second photomask of the plurality of photomasks, and patterning the semiconductor wafer with the second photonic module comprises forming a second doped region using the second photomask. 7. The method of claim 6 , wherein: patterning the semiconductor wafer with the first photonic module further comprises forming a first metal trace using a third photomask of the plurality of photomasks, and patterning the semiconductor wafer with the second photonic module further comprises forming a second metal trace using the third photomask. 8. The method of claim 7 , wherein: patterning the semiconductor wafer with the first photonic module further comprises forming a first region of germanium using a fourth photomask of the plurality of photomasks, and patterning the semiconductor wafer with the second photonic module further comprises forming a second region of germanium using the fourth photomask. 9. The method of claim 8 , wherein: patterning the semiconductor wafer with the first photonic module further comprises forming a first metal contact using a fifth photomask of the plurality of photomasks, and patterning the semiconductor wafer with the second photonic module further comprises forming a second metal contact using the fifth photomask. 10. The method of claim 1 , wherein each of the first and second photonic modules, when patterned, further comprises an out-of-plane optical coupler optically coupled to the optical distribution network. 11. The method of claim 1 , wherein the optical distribution network, when patterned, is configured to selectively place the first neighboring photonic module in optical communication with the second neighboring photonic module. 12. The method of claim 1 , wherein each of the first and second photonic modules, when patterned, further comprises: third and fourth boundaries, wherein the first and second boundaries are opposite to one another and the third and fourth boundaries are opposite to one another; a third optical waveguide optically coupling the optical distribution network to a third neighboring photonic module of the plurality of photonic modules, the third neighboring photonic module being adjacent to the third boundary; and a fourth optical waveguide optically coupling the optical distribution network to a fourth neighboring photonic module of the plurality of photonic modules, the fourth neighboring photonic module being adjacent to the fourth boundary. 13. The method of claim 12 , wherein the optical distribution network, when patterned, is configured to selectively place the first neighboring photonic module in optical communication with the second neighboring photonic module or the third neighboring photonic module. 14. The method of claim 1 , wherein the optical distribution network, when patterned, comprises a plurality of optical switches. 15. The method of claim 1 , wherein the first and second photonic modules, when patterned, are adjacent to one another such that the second photonic module is the first neighboring photonic module for the first photonic module. 16. The method of claim 1 , wherein the semiconductor wafer has a diameter of 150 mm, 300 mm, or 450 mm. 17. The method of claim 1 , further comprising, subsequent to patterning the semiconductor wafer with the second photonic module, dicing the semiconductor wafer to obtain a photonic substrate having N×M photonic modules, where N≥1 and M≥1. 18. The method of claim 1 , wherein: patterning the semiconductor wafer with the first photonic module comprises forming a first plurality of electrical connections configured for connection to a first die, and patterning the semiconductor wafer with the second photonic module comprises forming a second plurality of electrical connections configured for connection to a second die.

Assignees

Inventors

Classifications

  • using lasers · CPC title

  • Multiplexers; Demultiplexers · CPC title

  • Wavelength-division multiplex systems · CPC title

  • by etching · CPC title

  • forming wavelength selective elements, e.g. multiplexer, demultiplexer · CPC title

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What does patent US12092866B2 cover?
Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing t…
Who is the assignee on this patent?
Lightmatter Inc
What technology area does this patent fall under?
Primary CPC classification G02B6/12004. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 17 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).