Microcontroller circuit, corresponding device, system and method of operation

Patent metadata

Field	Value
Publication number	US-12088429-B2
Application number	US-202217677113-A
Country	US
Kind code	B2
Filing date	Feb 22, 2022
Priority date	Mar 8, 2021
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.

First claim

What is claimed is:

1. A circuit, comprising:
a first memory and a second memory;
a processor coupled to the first memory and the second memory, the processor configured to:
generate an output sequence comprising binary values encoding an outgoing Controller Area Network (CAN) frame according to a CAN protocol,
process the output sequence to detect a sequence of ordered pulse-width modulated (PWM) periods, each PWM period comprising a first portion having a dominant state and a second portion having a recessive state, each PWM period having a respective total duration and a respective duty-cycle value, wherein the processing the output sequence comprises:
detecting a start-of-frame bit having a dominant value in the output sequence;
counting a first number of consecutive bits having a dominant value in the output sequence until detecting a first bit having a recessive value;
counting a second number of consecutive bits having a recessive value in the output sequence until detecting a first bit having a dominant value; and
repeating the counting the first number and the counting the second number until having detected and processed an end-of-frame field in the output sequence,

store a set of ordered first values indicative of a first parameter of the PWM periods in the sequence of ordered PWM periods in the first memory, and
store a set of ordered second values indicative of a second parameter of the PWM periods in the sequence of ordered PWM periods in the second memory, wherein the first parameter and the second parameter define a shape of the PWM periods; and

a timer circuit comprising:
a first register configured to read from the first memory and store a value indicative of the first parameter of a current PWM period in the sequence of ordered PWM periods;
a counter circuit configured to:
increase an internal count number and reset the internal count number as a function of the value stored in the first register,
trigger reading from the first memory, and
trigger storing into the first register a subsequent value indicative of the first parameter of a subsequent PWM period in the sequence of ordered PWM periods as a function of the value stored in the first register; and

a second register configured to:
read from the second memory and store a value indicative of the second parameter of the current PWM period,
compare the internal count number of the counter circuit to the value stored into the second register,
drive an output pin of the circuit to a dominant value or to a recessive value as a function of the comparing the internal count number of the counter circuit to the value stored into the second register, the output pin providing an output PWM signal comprising the sequence of ordered PWM periods,
read from the second memory, and
store a subsequent value indicative of the second parameter of a subsequent PWM period in the sequence of ordered PWM periods in response to the internal count number of the counter circuit reaching the value stored into the second register or in response to the internal count number of the counter circuit reaching the value stored into the first register.

2. The circuit of claim 1 , wherein the first parameter of the PWM periods is the total duration of the PWM periods and the second parameter of the PWM periods is the duration of the first portions of the PWM periods.

3. The circuit of claim 2 , wherein the counter circuit is configured to:
increase an internal count number until reaching the value stored in the first register;
reset the internal count number in response to the internal count number reaching the value stored into the first register;
trigger reading from the first memory; and
trigger storing into the first register a subsequent value indicative of the total duration of a subsequent PWM period in the sequence of ordered PWM periods.

4. The circuit of claim 3 , wherein the second register is configured to:
drive the output pin of the circuit to a dominant value in response to the internal count number of the counter circuit being lower than the value stored in the second register; and
drive the output pin of the circuit to a recessive value in response to the internal count number of the counter circuit exceeding the value stored into the second register.

5. The circuit of claim 1 , wherein generating the output sequence comprises:
generating a raw CAN frame comprising an identification field, a data length code field, a payload field, and one or more control bits;
applying bit stuffing processing to the raw CAN frame to produce a bit stuffed raw CAN frame;
calculating a cyclic redundancy check (CRC) code as a function of the bit stuffed raw CAN frame; and
inserting the calculated CRC code into the bit stuffed raw CAN frame.

6. The circuit of claim 1 , further comprising:
a first direct memory access (DMA) controller configured to execute a DMA memory transfer of a subsequent first value of the set of ordered first values from the first memory to the first register in response to the internal count number of the counter circuit reaching the value stored into the first register; and
a second DMA controller configured to execute a DMA memory transfer of a subsequent second value of the set of ordered second values from the second memory to the second register in response to the internal count number of the counter circuit reaching the value stored into the second register or in response to the internal count number of the counter circuit reaching the value stored into the first register.

7. The circuit of claim 6 , wherein the processor is configured to:
count a number of the PWM periods in the sequence of ordered PWM periods;
configure the first DMA controller to execute a number of DMA transfers from the first memory to the first register equal to the counted number of PWM periods; and
configure the second DMA controller to execute a number of DMA transfers from the second memory to the second register equal to the counted number of PWM periods.

8. The circuit of claim 7 , wherein the first DMA controller or the second DMA controller are configured to issue an interrupt signal towards the processor in response to the respective number of DMA transfers executed being equal to the counted number of PWM periods.

9. The circuit of claim 1 , wherein the processor is configured to:
store into the first memory an additional last value of the set of ordered first values, the additional last value being higher than any other value stored into the first memory; and
store into the second memory an additional last value of the set of ordered second values, the additional last value being equal to zero.

10. The circuit of claim 1 , further comprising a third memory and a fourth memory, wherein the timer circuit further includes:
an edge detector circuit coupled to an input pin of the circuit, the input pin configured to receive an input PWM signal conveying an incoming CAN frame encoded according to a CAN protocol, the edge detector circuit configured to provide a first output signal indicative of falling edges detected in the input PWM signal and a second output signal indicative of rising edges detected in the input PWM signal;
a third register configured to capture a current count number of the counter circuit in response to a falling edge detected in the PWM signal; and
a fourth register configured to capture a current count number of the counter circuit in response to a rising edge detected in the PWM signal, wherein the counter circuit is configured to reset the internal count number in response to a falling edge detected in the input PWM signal.

11. The circuit of claim 10 , wherein the ci

Assignees

• St Microelectronics Des & Appl
• Stmicroelectronics Application Gmbh

Inventors

• Rennig Fred
• Dvorak Vaclav

Classifications

• H04L12/40006 Primary

  Architecture of a communication node (current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90) · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H04L2012/40215

  Controller Area Network CAN · CPC title

• H04L2012/40273

  the transportation system being a vehicle · CPC title

• B60R16/023

  for transmission of signals between vehicle parts or subsystems · CPC title