Clock sustain in the absence of a reference clock in a communication system

Patent metadata

Field	Value
Publication number	US-10250376-B2
Application number	US-201715411801-A
Country	US
Kind code	B2
Filing date	Jan 20, 2017
Priority date	Jan 29, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

First claim

The invention claimed is:

1. A slave node transceiver for low latency communication, comprising:
upstream transceiver circuitry to receive a signal transmitted over a bus from an upstream device;
clock circuitry to generate a clock signal at the slave node transceiver based on sync portions of the signal, wherein timing of the receipt and provision of signals over the bus by the slave node transceiver is based on the clock signal;
peripheral device communication circuitry to provide output signals to one or more peripheral devices; and
sustain circuitry to determine that a predetermined number of sync portions have not been received in a predetermined time interval, and in response to the determination, cause the attenuation of the output signals.

2. The slave node transceiver of claim 1 , wherein the sync portions of the signal are included in synchronization control frames of the signal.

3. The slave node transceiver of claim 1 , wherein the peripheral device communication circuitry includes an Inter-Integrated Circuit Sound (I2S) transceiver, a Time Division Multiplex (TDM) transceiver, a Pulse Density Modulation (PDM) transceiver, an Inter-Integrated Circuit (I2C) transceiver, or a General Purpose Input/Output (GPIO) pin.

4. The slave node transceiver of claim 1 , wherein the clock circuitry includes a phase locked loop (PLL), and the PLL continues to run during attenuation of the output signals.

5. The slave node transceiver of claim 4 , wherein the clock circuitry is not to attempt relock of the PLL during attenuation of the output signals.

6. The slave node transceiver of claim 1 , wherein the attenuation of the output signals includes the reduction in value of at least one output signal to zero over a predetermined time interval.

7. The slave node transceiver of claim 1 , wherein the sustain circuitry is to cause the slave node transceiver to reset after attenuation of the output signals.

8. The slave node transceiver of claim 1 , wherein the sustain circuitry is further to, after reset, determine that a predetermined number of sync portions have been received in a predetermined time interval and, in response, cause the slave node transceiver to communicate over the bus.

9. The slave node transceiver of claim 1 , wherein the bus is a two-wire bus.

10. The slave node transceiver of claim 1 , further comprising:
downstream transceiver circuitry to provide a signal downstream over the bus toward a downstream device.

11. The slave node transceiver of claim 1 , further comprising:
power circuitry to receive a voltage bias over the bus from the upstream device.

12. The slave node transceiver of claim 1 , wherein the upstream device is another slave node transceiver.

13. The slave node transceiver of claim 1 , wherein the upstream device is a master node transceiver.

14. A low latency communication system, comprising:
a master node transceiver; and
a plurality of slave node transceivers coupled to the master node transceiver in a daisy chain bus,
wherein individual ones of the slave node transceivers generate a local clock signal based on synchronization information sent downstream through the bus, individual ones of the slave node transceivers provide local outputs to locally connected peripheral devices, and individual ones of the slave node transceivers are to, upon determination that the synchronization information is inadequate to generate the local clock signal, attenuate the local outputs provided to the locally connected peripheral devices.

15. The low latency communication system of claim 14 , wherein the daisy chain bus is a two-wire bus.

16. The low latency communication system of claim 14 , wherein determine that the synchronization information is inadequate to generate the local clock signal includes determine that an insufficient number of synchronization signals has been received to lock a local phase locked loop (PLL).

17. The low latency communication system of claim 14 , wherein one or more of the locally connected peripheral devices includes an audio output device or an audio input device.

18. A method of powering down a slave node transceiver on a low latency communication bus, comprising:
identifying, by a slave node transceiver, synchronization portions of a signal received from the bus;
determining, by the slave node transceiver, that the synchronization portions are not adequate to generate a clock signal local to the slave node transceiver; and
in response to determining that the synchronization portions are not adequate, gradually decreasing an amplitude of an output from the slave node transceiver to a peripheral device.

19. The method of claim 18 , wherein determining that the synchronization portions are not adequate includes determining that no synchronization portion has been received in a predetermined time interval.

20. The method of claim 18 , wherein the output from the slave node transceiver to a peripheral device is an Inter-Integrated Circuit Sound (I2S) output.

Assignees

• Analog Devices Inc

Inventors

• Hooper William
• Lahr Lewis F

Classifications

• H04L12/403

  with centralised control, e.g. polling · CPC title

• H04R2420/07

  Applications of wireless loudspeakers or wireless microphones · CPC title

• H04R5/00

  Stereophonic arrangements (stereophonic pick-ups H04R9/16, H04R11/12, H04R17/08, H04R19/10) · CPC title

• H04H60/00

  Arrangements for broadcast applications with a direct linking to broadcast information or broadcast space-time; Broadcast-related systems · CPC title

• H04R2499/13

  Acoustic transducers and sound field adaptation in vehicles · CPC title