Circuit and method to enhance efficiency of semiconductor device

Patent metadata

Field	Value
Publication number	US-12088307-B2
Application number	US-202318356218-A
Country	US
Kind code	B2
Filing date	Jul 21, 2023
Priority date	Oct 13, 2020
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

First claim

What is claimed is:

1. A circuit, comprising:
a converter for converting a first predetermined clock signal to a first predetermined digital code based on a sampling clock signal, and converting a second predetermined clock signal to the second predetermined digital code based on a sampling clock signal;
a period calculator, for receiving the first predetermined digital code and the second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code, the first predetermined digital code having a first predetermined period value, the second predetermined digital code having a second predetermined period value; and
a pulse width calculator, for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to a linear extrapolation equation of a transfer curve associated with the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

2. The circuit of claim 1 , the pulse width calculator is configured for calculating an offset value k, the offset value k is expressed as:

k
=

T
⁢

D
2

-

U
⁢
T
⁢

D
1

D
2

-

D
1

where T is the first predetermined period value, UT is the second predetermined period value, and U>1, D 1 is the first calculated period value, and D 2 is the second calculated period value.

3. The circuit of claim 2 , wherein the linear extrapolation equation is expressed as:

y
=

T
⁡
(

U
-
1

)

D
2

-

D
1

⁢
V

+
k

=

T
⁡
(

U
-
1

)

D
2

-

D
1

⁢
V

+

T
⁡
(

D
2

-

U
⁢

D
1

)

D
2

-

D
1

where y is the predetermined pulse width, V is the first pulse width code.

4. The circuit of claim 3 , wherein the first pulse width code V is expressed as:

V
=

y
T

×

D
2

-

D
1

U
-
1

-

D
2

-

U
⁢

D
1

U
-
1

.

5. The circuit of claim 4 , further comprising a first operator for comparing the first pulse width code and a check value.

6. The circuit of claim 5 , further comprising a second operator for calculating a modified value, wherein the modified value is equal to the first pulse width code minus the check value.

7. The circuit of claim 6 , wherein the pulse width calculator is configured for calculating a second pulse width code W, the second pulse width code W is expressed as:

W
=

y

(

U
-
1

)

⁢
T

×

(

D

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Li Mao-Ruei
• Tsai Ming Hsien
• Sheen Ruey-Bin

Classifications

• G04F10/04

  by counting pulses or half-cycles of an AC {(G04F10/005 takes precedence)} · CPC title

• G06F30/337

  Design optimisation · CPC title

• G11C16/32

  Timing circuits · CPC title

• H03L7/06

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title