Deep trench isolations and methods of forming the same

Patent metadata

Field	Value
Publication number	US-12087801-B2
Application number	US-202217646765-A
Country	US
Kind code	B2
Filing date	Jan 3, 2022
Priority date	Aug 31, 2015
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

First claim

What is claimed is:

1. An image sensor structure comprising:
a semiconductor substrate having a major surface;
a deep trench isolation region extending from the major surface into the semiconductor substrate, wherein the deep trench isolation region surrounds a plurality of pixel regions and comprises:
a vertical sidewall extending from the major surface into the semiconductor substrate, wherein the vertical sidewall is substantially perpendicular to the major surface; and
a straight bottom surface connected to the vertical sidewall;

a first dielectric layer comprising a first portion in the deep trench isolation region, and a second portion outside of the deep trench isolation region, with the second portion having a horizontal top surface;
a second dielectric layer over the first dielectric layer, wherein a part of the second dielectric layer is in the deep trench isolation region, and wherein in a cross-section of the image sensor structure, a bottommost end of the part of the second dielectric layer is lower than the major surface and higher than a bottom end of the vertical sidewall; and
an isolation region in the deep trench isolation region.

2. The image sensor structure of claim 1 further comprising a core, with the first dielectric layer comprising opposing portions on opposite sides of the core, wherein the core comprises:
a widest portion at a level below the major surface; and
an upper portion over and narrower than the widest portion.

3. The image sensor structure of claim 2 , wherein the core further comprises a lower portion lower than, and narrower than, the widest portion.

4. The image sensor structure of claim 1 , wherein the straight bottom surface is horizontal, and the image sensor structure further comprises a slant-and-straight surface joined to the straight bottom surface.

5. The image sensor structure of claim 4 , wherein the slant-and-straight surface has a tilt angle equal to about 54.7 degrees.

6. The image sensor structure of claim 1 , wherein the vertical sidewall has a tilt angle greater than about 88 degrees.

7. The image sensor structure of claim 1 further comprising a transistor formed at a front surface of the semiconductor substrate, wherein the major surface is a back surface of the semiconductor substrate.

8. The image sensor structure of claim 7 further comprising a front-side trench isolation region extending from the front surface of the semiconductor substrate into the semiconductor substrate.

9. The image sensor structure of claim 8 , wherein the front-side trench isolation region is vertically aligned to, and is spaced apart from, the deep trench isolation region by a portion of the semiconductor substrate.

10. The image sensor structure of claim 1 further comprising a transistor formed at a front surface of the semiconductor substrate, wherein the deep trench isolation region extends from the front surface into the semiconductor substrate.

11. An image sensor structure comprising:
a semiconductor substrate;
an isolation structure extending into the semiconductor substrate, the isolation structure comprising:
a first dielectric liner; and
a second dielectric liner over the first dielectric liner, wherein the first dielectric liner and the second dielectric liner are formed of different dielectric materials;

a core, wherein each of the first dielectric liner and the second dielectric liner comprises opposing portions on opposing sides of the core, wherein the first dielectric liner comprises a portion overlapped by the core; and
an oxide layer comprising:
a first portion extending into the second dielectric liner to contact the core; and
a second portion directly overlapping the semiconductor substrate and the first dielectric liner and the second dielectric liner.

12. The image sensor structure of claim 11 , wherein the core comprises a topmost end lower than a top surface of the semiconductor substrate, and wherein the core comprises:
an intermediate portion having a first width;
an upper portion over the intermediate portion, the upper portion having a second width smaller than the first width; and
a lower portion under the intermediate portion, the lower portion having a third width smaller than the first width.

13. The image sensor structure of claim 11 , wherein the core is fully encircled by the second dielectric liner.

14. The image sensor structure of claim 11 , wherein the opposing portions of the first dielectric liner has a first spacing from each other at a first level same as a top surface level of the semiconductor substrate, and a second spacing from each other at a second level lower than the top surface level of the semiconductor substrate, and wherein the second spacing is greater than the first spacing.

15. The image sensor structure of claim 11 , wherein the core is a metal core.

16. The image sensor structure of claim 11 , wherein the core is a metal core.

17. An image sensor structure comprising:
a semiconductor substrate comprising a top surface;
a filling material;
an isolation structure extending into the semiconductor substrate, the isolation structure comprising:
a portion of the filling material;
a first dielectric layer comprising a bottom portion overlapped by the filling material, and sidewalls on opposing side of the filling material, wherein the first dielectric layer comprises:
a vertical sidewall having a tilt angle greater than about 88 degrees;
a horizontal bottom surface; and
a slant-and-straight bottom surface joining the horizontal bottom surface to the vertical sidewall; and

a core formed of a different material than the first dielectric layer, with the first dielectric layer comprising opposing portions on opposite sides of the core, wherein a widest part of the core is at a level lower than the top surface of the semiconductor substrate, and wherein the core comprises an upper part higher than the widest part, and a lower part lower than the widest part, and wherein both of the upper part and the lower part are narrower than the widest part.

18. The image sensor structure of claim 17 , wherein the slant-and-straight bottom surface has an additional tilt angle equal to about 54.7 degrees.

19. The image sensor structure of claim 17 , wherein the widest part of the core is at an intermediate level of the core.

20. The image sensor structure of claim 17 , wherein the core is a metal core.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chou Cheng-Hsien
• Lai Chih-Yu
• Chou Shih Pei
• Chiang Yen-Ting
• Tseng Hsiao-Hui
• Tsai Min-Ying

Classifications

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/01

  Manufacture or treatment · CPC title

• H10W10/00 Primary

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title