Solid-state imaging element and electronic device

Patent metadata

Field	Value
Publication number	US-12087799-B2
Application number	US-201917273585-A
Country	US
Kind code	B2
Filing date	Sep 5, 2019
Priority date	Sep 19, 2018
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

The present disclosure relates to a solid-state imaging element and an electronic device capable of increasing the capacitance of a charge holding unit. The solid-state imaging element includes a pixel including a photodiode, an FD that accumulates charges generated in the photodiode, and a charge holding unit that is connected in parallel with the FD. The charge holding unit includes a wiring capacitance formed by parallel running of a first wiring connected to a first potential and a second wiring connected to a second potential different from the first potential. The present disclosure can be applied to a solid-state imaging element that performs global shutter type imaging.

First claim

What is claimed is:

1. A solid-state imaging element, comprising:
a pixel, including:
a photodiode;
a floating diffusion that accumulates charges generated in the photodiode; and
a charge holding unit,

wherein the charge holding unit includes a wiring capacitance formed by a first wiring connected to a first potential and a second wiring connected to a second potential different from the first potential,
wherein, in a plan view, at least a part of the first wiring and at least a part of the second wiring are surrounded by a third wiring that is connected to a fixed potential.

2. The solid-state imaging element according to claim 1 , wherein a bent portion of the first wiring and the second wiring is formed in any of an L-shape, a T-shape, a U-shape, and a cross shape.

3. The solid-state imaging element according to claim 2 , wherein the first wiring and the second wiring are formed in one or more wiring layers, and
wherein a part of the first wiring and the second wiring is formed directly above the photodiode.

4. The solid-state imaging element according to claim 3 , wherein a part of the first wiring and the second wiring is formed in the wiring layer of a first layer directly above a substrate.

5. The solid-state imaging element according to claim 4 , wherein a part of the first wiring and the second wiring is formed so that a line width and a distance between the first wiring and the second wiring are narrower than a wavelength to be captured.

6. The solid-state imaging element according to claim 3 , wherein
the second wiring is formed as at least one of an FD wiring connected to the FD, a fixed potential line, and a control line of a pixel transistor.

7. The solid-state imaging element according to claim 6 , wherein
a potential of the fixed potential line includes GND.

8. The solid-state imaging element according to claim 6 , wherein
the pixel transistor includes a transfer transistor.

9. The solid-state imaging element according to claim 6 , wherein the first wiring runs in parallel with the floating diffusion wiring to form a coupling capacitance with the floating diffusion.

10. The solid-state imaging element according to claim 9 , wherein the first wiring and the floating diffusion wiring are formed in a region surrounded by the fixed potential line or the control line.

11. The solid-state imaging element according to claim 10 , wherein the solid-state imaging element includes a plurality of pixels, and
wherein the first wiring and the second wiring are formed in a same wiring layout in all the pixels.

12. The solid-state imaging element according to claim 11 , wherein the first wiring and the second wiring are in a same wiring layer as one another and form the wiring capacitance in that same wiring layer.

13. The solid-state imaging element according to claim 11 , wherein the first wiring and the second wiring are in different wiring layers from one another and form the wiring capacitance between the different wiring layers.

14. The solid-state imaging element according to claim 2 , wherein the first wiring and the second wiring are in a same wiring layer as one another and form the wiring capacitance in a same wiring layer and between different wiring layers.

15. The solid-state imaging element according to claim 11 ,
wherein the first wiring and the second wiring are in different wiring layers,
wherein extensions of the first wiring extend in a first direction,
wherein extensions of the second wiring extend in a second direction, and
wherein the first direction is perpendicular to the second direction.

16. The solid-state imaging element according to claim 11 , wherein a film having a high dielectric constant is used as an insulating film between the first wiring and the second wiring.

17. The solid-state imaging element according to claim 2 , wherein a diffusion layer is provided in a substrate, wherein the substrate is connected to the first wiring, and wherein the diffusion layer provided in the substrate has a larger area than another diffusion layer forming the pixel transistor.

18. A solid-state imaging element, comprising:
a pixel, including:
a photodiode;
a floating diffusion that accumulates charges generated in the photodiode; and
a charge holding unit that is connected in parallel with the floating diffusion,

wherein the charge holding unit includes a wiring capacitance formed by parallel running of a first wiring connected to a first potential and a second wiring connected to a second potential different from the first potential,
wherein the first wiring and the second wiring each have an extending portion extending in a first direction and a bent portion extending in a second direction,
wherein the bent portion of the first wiring and the second wiring is formed in any of an L-shape, a T-shape, a U-shape, and a cross shape,
wherein the first wiring and the second wiring are formed in one or more wiring layers,
wherein a part of the first wiring and the second wiring is formed directly above the photodiode,
wherein a part of the first wiring and the second wiring is formed in the wiring layer of a first layer directly above a substrate,
wherein a part of the first wiring and the second wiring is formed so that a line width and a distance between the first wiring and the second wiring are narrower than a wavelength to be captured, and
wherein each of a part of the first wiring and the second wiring is formed in a comb shape facing each other in a same wiring layer.

19. An electronic device, comprising:
a solid-state imaging element, including:
a pixel, including:
a photodiode;
a floating diffusion that accumulates charges generated in the photodiode; and
a charge holding unit,

wherein the charge holding unit includes a wiring capacitance formed by a first wiring connected to a first potential and a second wiring connected to a second potential different from the first potential,
wherein, in a plan view, at least a part of the first wiring and at least a part of the second wiring are surrounded by a third wiring that is connected to a fixed potential.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Otake Yusuke
• Wakano Toshifumi
• Murase Takuro

Classifications

• H10F39/8037

  the integrated elements comprising a transistor · CPC title

• H10F39/811 Primary

  Interconnections · CPC title

• H10F39/805

  Coatings · CPC title

• H10F39/153

  Two-dimensional or three-dimensional array CCD image sensors · CPC title

• H10F39/18 Primary

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title