Integrated circuit device

Patent metadata

Field	Value
Publication number	US-12087766-B2
Application number	US-202117383749-A
Country	US
Kind code	B2
Filing date	Jul 23, 2021
Priority date	Dec 23, 2020
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a fin-type active region extending longitudinally in a first lateral direction on a substrate;
a nanosheet disposed at a position apart from a fin top surface of the fin-type active region in a vertical direction, and facing the fin top surface;
an inner insulating spacer between the substrate and the nanosheet;
a gate line including a main gate portion and a sub-gate portion, the main gate portion extending longitudinally in a second lateral direction on the nanosheet, the sub-gate portion being integrally connected to the main gate portion and between the substrate and the nanosheet, wherein the second lateral direction intersects with the first lateral direction; and
a source/drain region facing the sub-gate portion with the inner insulating spacer therebetween in the first lateral direction, the source/drain region being in contact with the inner insulating spacer and the nanosheet, the source/drain region including a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body toward an inside of the source/drain region,
wherein the at least one stacking fault surface comprises a plurality of stacking fault surfaces, and
wherein a density of the plurality of stacking fault surfaces increases toward a center of the source/drain region.

2. The integrated circuit device as claimed in claim 1 , wherein the at least one lower stacking fault surface includes a first lower stacking fault surface and a second lower stacking fault surface, which extend in directions that intersect with each other.

3. The integrated circuit device as claimed in claim 1 , wherein the single crystalline semiconductor body includes single crystalline silicon doped with n-type impurities.

4. The integrated circuit device as claimed in claim 1 , wherein the at least one lower stacking fault surface includes a first lower stacking fault surface having an angle of about 50° to about 60° with respect to a straight line in the first lateral direction.

5. The integrated circuit device as claimed in claim 1 , wherein the at least one lower stacking fault surface includes a first lower stacking fault surface having an angle of about 30° to about 40° with respect to a straight line in the vertical direction.

6. The integrated circuit device as claimed in claim 1 , wherein the at least one lower stacking fault surface is parallel to a {111} crystal plane of the single crystalline semiconductor body.

7. The integrated circuit device as claimed in claim 1 , further comprising an outer insulating spacer covering a sidewall of the gate line, the outer insulating spacer being in contact with the source/drain region,
wherein the source/drain region further includes at least one upper stacking fault surface extending from the outer insulating spacer toward an inside of the source/drain region.

8. The integrated circuit device as claimed in claim 7 , wherein the at least one upper stacking fault surface includes a first upper stacking fault surface having an angle of about 50° to about 60° with respect to a straight line in the first lateral direction.

9. The integrated circuit device as claimed in claim 7 , wherein the at least one upper stacking fault surface includes a first upper stacking fault surface and a second upper stacking fault surface, which extend in directions that intersect with each other.

10. The integrated circuit device as claimed in claim 7 , wherein the at least one upper stacking fault surface is parallel to a {111} crystal plane of the single crystalline semiconductor body.

11. The integrated circuit device as claimed in claim 1 , wherein:
each of the nanosheet and the substrate includes a silicon film, and
a first lattice constant of silicon lattices included in at least a partial region of the nanosheet is higher than a second lattice constant of silicon lattices included in at least a partial region of the substrate.

12. An integrated circuit device, comprising:
a fin-type active region extending longitudinally in a first lateral direction on a substrate;
a source/drain region on the fin-type active region;
first and second nanosheet stacks on a fin top surface of the fin-type active region, the first and second nanosheet stacks being apart from each other with the source/drain region therebetween in the first lateral direction, each of the first and second nanosheet stacks including a plurality of nanosheets overlapping each other in a vertical direction;
a first gate line surrounding the first nanosheet stack on the fin-type active region, the first gate line extending longitudinally in a second lateral direction intersecting with the first lateral direction;
a second gate line surrounding the second nanosheet stack on the fin-type active region, the second gate line extending longitudinally in the second lateral direction;
a first insulating spacer between the first gate line and the source/drain region; and
a second insulating spacer between the second gate line and the source/drain region,
wherein the source/drain region includes a single crystalline semiconductor body and a plurality of stacking fault surfaces linearly extending from the first insulating spacer and the second insulating spacer through the single crystalline semiconductor body toward an inside of the source/drain region, and

wherein a density of the plurality of stacking fault surfaces increases toward a center of the source/drain region.

13. The integrated circuit device as claimed in claim 12 , wherein:
each of the first insulating spacer and the second insulating spacer includes an inner insulating spacer and an outer insulating spacer, the inner insulating spacer being between the substrate and the plurality of nanosheets, the inner insulating spacer contacting the source/drain region, the outer insulating spacer covering a sidewall of any one of the first gate line and the second gate line on the plurality of nanosheets, and the outer insulating spacer contacting the source/drain region, and
the plurality of stacking fault surfaces include:
at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body toward an inside of the source/drain region, and
at least one upper stacking fault surface extending from the outer insulating spacer toward the inside of the source/drain region.

14. The integrated circuit device as claimed in claim 12 , wherein the plurality of stacking fault surfaces include a first stacking fault surface and a second stacking fault surface, which extend in directions that intersect with each other.

15. The integrated circuit device as claimed in claim 12 , wherein an angle between at least one of the plurality of stacking fault surfaces and a straight line in the first lateral direction is in a range of about 50° to about 60°.

16. The integrated circuit device as claimed in claim 12 , wherein the plurality of stacking fault surfaces include first and second stacking fault surfaces, which extend in directions that intersect with each other, and
an angle between each of the first and second stacking fault surfaces and a straight line in the vertical direction is in a range of about 30° to about 40°.

17. The integrated circuit device as claimed in claim 12 , wherein at least one of the plurality of stacking fault surfaces is parallel to a {111} crystal plane of the single crystalline semiconductor body.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Sujin
• Kim Kihwan
• Jang Sunguk
• Cho Youngdae

Classifications

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title