Gallium nitride integrated circuits including non-gold-based metallic materials

Patent metadata

Field	Value
Publication number	US-12087713-B2
Application number	US-202218148982-A
Country	US
Kind code	B2
Filing date	Dec 30, 2022
Priority date	Oct 22, 2019
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

First claim

The invention claimed is:

1. A device having a monolithic microwave integrated circuit comprises:
a substrate having:
a barrier layer disposed on the substrate, the barrier layer including an aluminum gallium nitride (AlGaN) material and including a drain region, a source region, and a gate region; and
a channel layer disposed between a surface of the substrate and the barrier layer, the channel layer including a gallium nitride (GaN) material;
a gate electrical contact disposed on the gate region of the barrier layer, the gate electrical contact including one or more non-gold-based metallic materials;
a source electrical contact disposed on the source region of the barrier layer, the source electrical contact including a non-gold-based metallic material of the one or more non-gold-based metallic materials;
a drain electrical contact disposed on the drain region of the barrier layer, the drain electrical contact including the non-gold-based metallic material of the one or more non-gold-based metallic materials; and
a capacitor including a first plate, a second plate, and a dielectric material disposed between the first plate and the second plate, wherein at least a portion of the first plate is disposed on at least one of the channel layer or the barrier layer; the second plate is disposed on the dielectric material; and the first plate and the second plate include the non-gold-based metallic material of the one or more non-gold-based metallic materials.

2. The device of claim 1 , wherein a portion of the first plate is disposed over and in contact with the source electrical contact.

3. The device of claim 1 , wherein: the dielectric material is part of a dielectric material layer that is disposed over at least a portion of the barrier layer, at least a portion of the channel layer, and electrical features disposed on at least one of the barrier layer or the channel layer; the one or more non-gold-based metallic materials include an aluminum-containing material having at least 95% Al by weight; and the dielectric material layer includes silicon dioxide (SiO 2 ) or disilicon trinitride (Si 2 N 3 ).

4. The device of claim 3 , comprising: a connector coupled to the source electrical contact, the connector including a first portion that passes through the dielectric material layer and a second portion that is disposed on the dielectric material layer, the connector including the non-gold-based metallic material of the one or more non-gold-based metallic materials.

5. The device of claim 1 , comprising: an impedance device disposed on at least one of the channel layer or the barrier layer; and a connector coupled to the impedance device and the drain electrical contact, the connector including an additional non-gold based metallic material.

6. The device of claim 1 , comprising: a via that passes through the substrate and at least one of the channel layer or the barrier layer, the via being filed at least partially with the non-gold-based metallic material of the one or more non-gold-based metallic materials and the via is coupled with an electrical feature disposed on at least one of the barrier layer or the channel layer.

7. The device of claim 6 , wherein the via is coupled with the source electrical contact.

8. The device of claim 1 , wherein the one or more non-gold-based metallic materials include at least one of aluminum (Al), titanium (Ti), or titanium nitride (TiN).

9. The device of claim 8 , wherein:
the gate electrical contact includes at least one layer of Al and at least one layer of TiN;
the source electrical contact includes at least one layer of Al and at least one layer of Ti; and
the drain electrical contact includes at least one layer of Al and at least one layer of Ti.

10. The device of claim 1 , wherein the gate electrical contact has a length from about 100 nm to about 300 nm.

11. The device of claim 10 , wherein: the substrate includes silicon carbide (SiC); and the device includes an additional gate electrical contact disposed on an additional gate region of the barrier layer, the additional gate electrical contact including the non-gold-based metallic material of the one or more non-gold-based metallic materials and a length of the additional gate electrical contact is from about 500 nm to about 1000 nm.

12. The device of claim 1 , wherein: the substrate is a sapphire-containing substrate, a silicon carbide- (SiC) containing substrate, or a silicon- (Si) containing substrate; and a thickness of the substrate is no greater than about 200 micrometers.

13. The device of claim 1 , wherein the surface of the substrate that the channel layer and the barrier layer are disposed over is a first surface of the substrate and the substrate includes a second surface that is at least substantially parallel to the first surface; and the device comprises a non-gold-based metal layer that is disposed on the second surface.

14. A device having a monolithic microwave integrated circuit comprises:
a substrate having:
a barrier layer disposed on the substrate, the barrier layer including an aluminum gallium nitride (AlGaN) material and including a drain region, a source region, and a gate region; and
a channel layer disposed between a surface of the substrate and the barrier layer, the channel layer including a gallium nitride (GaN) material;
a gate electrical contact disposed on the gate region of the barrier layer, the gate electrical contact including one or more non-gold-based metallic materials and having a length;
a source electrical contact disposed on the source region of the barrier layer, the source electrical contact including a non-gold-based metallic material of the one or more non-gold-based metallic materials;
a drain electrical contact disposed on the drain region of the barrier layer, the drain electrical contact including the non-gold-based metallic material of the one or more non-gold-based metallic materials;
one or more dielectric layers disposed on the gate electrical contact, the source electrical contact, and the drain electrical contact; and
one or more additional non-gold-based metallic features disposed in the one or more dielectric layers.

15. The device of claim 14 , wherein the length of the gate electrical contact is from about 100 nm to about 300 nm or from about 500 nm to about 1000 nm.

16. The device of claim 14 , comprising:
one or more first electronic components configured to operate at frequencies of at least 3 gigahertz (GHz); and
one or more second electronic components configured to operate at voltages of at least 50 volts (V).

17. The device of claim 14 , wherein the one or more dielectric layers include a plurality of dielectric layers and the device comprises:
a first portion of an interconnect device disposed within a first dielectric layer of the plurality of dielectric layers, the first portion of the interconnect device including the non-gold-based metallic material of the one or more non-gold-based metallic materials; and
a second portion of an interconnect device coupled to the first portion of the interconnect device and disposed within a second dielectric layer of the plurality of dielectric layers, the second portion of the interconnect device including the non-gold-based metallic material of the one or more non-gold-based metallic materials.

18. The device of claim 17 , wherein the interconnect device is coupled to the source electrical contact by a connector disposed in a third dielectric layer of the plurality of dielectric layers.

19. The device of claim 17 , co

Assignees

• Analog Devices Inc

Inventors

• Piedra Daniel
• Fiorenza James G
• Srivastava Puneet
• Proudman Andrew
• Flanders Kenneth
• Murphy Denis Michael
• Green Leslie P
• Stubler Peter R

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10D64/0116

  to Group III-V semiconductors · CPC title

• H10W44/251

  for monolithic microwave integrated circuits [MMIC] · CPC title

• H10W44/209

  Vertical interconnections, e.g. vias · CPC title