Method for fabricating an integrated circuit device

Patent metadata

Field	Value
Publication number	US-12087712-B2
Application number	US-202318123317-A
Country	US
Kind code	B2
Filing date	Mar 19, 2023
Priority date	May 28, 2020
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

First claim

What is claimed is:

1. A method for fabricating an integrated circuit device, comprising:
providing a substrate;
forming an integrated circuit area on said substrate, said integrated circuit area comprising a dielectric stack;
forming a seal ring in said dielectric stack and around a periphery of said integrated circuit area;
forming a trench around said seal ring and exposing a sidewall of said dielectric stack, wherein said trench is disposed within a scribe line;
forming a moisture blocking layer on said sidewall of said dielectric stack, thereby sealing a boundary between two adjacent dielectric films in said dielectric stack, wherein said moisture blocking layer is a composite layer comprising a silicon oxide layer and a silicon nitride layer on the silicon oxide layer;
performing an anisotropic etching process to etch said moisture blocking layer, thereby forming a moisture blocking spacer in said trench; and
depositing an inter-layer dielectric (ILD) film on said dielectric stack and said moisture blocking spacer, wherein said trench is filled with said ILD film and said moisture blocking spacer.

2. The method according to claim 1 , wherein said integrated circuit area comprises a radio-frequency (RF) circuit.

3. The method according to claim 1 , wherein said substrate is a silicon-on-insulator (SOI) substrate comprising a lower substrate, a buried oxide layer on the lower substrate, and a device layer on the buried oxide layer.

4. The method according to claim 3 , wherein said device layer comprises a silicon layer.

5. The method according to claim 3 , wherein said seal ring is electrically coupled to said lower substrate with a through contact that penetrates through said device layer and said buried oxide layer.

6. The method according to claim 1 , wherein said two adjacent dielectric films are two adjacent low-dielectric constant (low-k) dielectric films.

7. The method according to claim 1 , wherein said seal ring is a discontinuous seal ring.

8. The method according to claim 7 , wherein said seal ring is composed of interconnected metal lines and vias.

9. The method according to claim 8 , wherein said metal lines comprise a topmost copper metal line.

10. The method according to claim 9 , wherein said topmost copper metal line is a topmost damascene copper layer.

11. The method according to claim 9 further comprising:
after depositing said ILD film, forming a topmost dielectric film over said ILD film;
forming a topmost via layer penetrating through said topmost dielectric film to electrically connect with said topmost copper metal layer; and
forming an aluminum pad disposed on and electrically connected to said topmost via layer.

12. The method according to claim 11 further comprising:
forming a passivation layer covering a periphery of said aluminum pad and a top surface of said topmost dielectric film.

13. The method according to claim 12 , wherein said topmost dielectric film comprises silicon oxide.

14. The method according to claim 12 , wherein said passivation layer comprises polyimide or silicon oxide.

Assignees

• United Microelectronics Corp

Inventors

• Verma Purakh Raj
• Yang Kuo-Yuh
• Lin Chia-Huei
• Chang Chu-Chun

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title