Colored gratings in microelectronic structures

Patent metadata

Field	Value
Publication number	US-12087594-B2
Application number	US-202017124730-A
Country	US
Kind code	B2
Filing date	Dec 17, 2020
Priority date	Dec 17, 2020
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

Disclosed herein are colored gratings in microelectronic structures. For example, a microelectronic structure may include first conductive structures alternating with second conductive structures, wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures. In some embodiments, a microelectronic structure may include one or more unordered lamellar regions laterally spaced apart from and aligned with the first conductive structures.

First claim

The invention claimed is:

1. A microelectronic structure, comprising:
a metallization layer including a conductive structure;
a first unordered lamellar region laterally spaced apart from and aligned with a bottom portion of the conductive structure; and
a second unordered lamellar region above the first unordered lamellar region, wherein the second unordered lamellar region is laterally spaced apart from and aligned with a top portion of the conductive structure.

2. The microelectronic structure of claim 1 , wherein the first unordered lamellar region has a different unordered lamellar pattern than the second unordered lamellar region.

3. The microelectronic structure of claim 1 , wherein the metallization layer includes first spacer portions adjacent to the bottom portion of the conductive structure, and the first unordered lamellar region includes material having a same material composition as the first spacer portions.

4. The microelectronic structure of claim 3 , wherein the material is a first material, the second unordered lamellar region includes a second material different from the first material, and the second material is a dielectric material.

5. The microelectronic structure of claim 1 , wherein the metallization layer includes second spacer portions adjacent to the top portion of the conductive structure, and the second unordered lamellar region includes material having a same material composition as the second spacer portions.

6. The microelectronic structure of claim 1 , wherein the second unordered lamellar region includes material having a same material composition as the conductive structure.

7. The microelectronic structure of claim 1 , further comprising:
a device layer; and
additional metallization layers, wherein the metallization layer is between the device layer and the additional metallization layers.

8. A microelectronic structure, comprising:
a metallization layer including first conductive structures alternating with second conductive structures;
wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures.

9. The microelectronic structure of claim 8 , wherein an individual cap structure includes silicon and nitrogen.

10. The microelectronic structure of claim 8 , wherein individual ones of the first conductive structures have straight sidewalls.

11. The microelectronic structure of claim 8 , further comprising: transistor contacts; wherein individual ones of the first conductive structures are above and vertically aligned with individual ones of the transistor contacts.

12. The microelectronic structure of claim 11 , wherein the transistor contacts include one or more gate contacts.

13. The microelectronic structure of claim 11 , wherein the transistor contacts include one or more source/drain contacts.

14. The microelectronic structure of claim 11 , wherein the transistor contacts are in trenches, and the trenches also includes a metal oxide.

15. The microelectronic structure of claim 14 , wherein individual ones of the transistor contacts are between a first portion of metal oxide and a second portion of metal oxide in an individual trench.

16. The microelectronic structure of claim 8 , wherein the metallization layer is a first metallization layer over a device layer.

17. A computing device, comprising:
a die including a microelectronic structure, wherein the microelectronic structure includes first conductive structures alternating with second conductive structures, individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are aligned with the second conductive structures, and the top portions of the first conductive structures are aligned with the cap structures; and
a circuit board, wherein the die is communicatively coupled to the circuit board.

18. The computing device of claim 17 , wherein the first conductive structures and the second conductive structures are horizontally aligned with an unordered lamellar region.

19. The computing device of claim 18 , wherein the unordered lamellar region is part of a transition region of the die, under a guard ring of the die, or in a frame of the die.

20. The computing device of claim 17 , wherein the die is included in a package, and the package is communicatively coupled to the circuit board.

Assignees

• Intel Corp

Inventors

• Singh Gurpreet
• Han Eungnak
• Chandhok Manish
• Schenker Richard E
• Gstrein Florian
• Nyhus Paul A
• Wallace Charles Henry

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title