Methods for forming interconnect layers having tight pitch interconnect structures

Patent metadata

Field	Value
Publication number	US-9379010-B2
Application number	US-201414163323-A
Country	US
Kind code	B2
Filing date	Jan 24, 2014
Priority date	Jan 24, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.

First claim

What is claimed is:

1. A method of forming a microelectronic structure, comprising:
forming a dielectric layer on a substrate;
forming a first hardmask layer on the dielectric layer;
forming a plurality of backbone structures on the first hardmask layer;
forming side spacers adjacent sides of each of the plurality of backbone structures;
etching a portion of the first hardmask layer and a portion of the dielectric layer between adjacent side spacers between at least two adjacent backbone structures to form at least one first trench, without removing any of the plurality of backbone structures;
depositing a sacrificial material in the at least one first trench;
removing at least one backbone structure and etching a portion of the first hardmask layer and the dielectric layer which resided below the at least one backbone structure to form at least one second trench, without removing the sacrificial material in the at least one first trench;
depositing a fill material in the at least one second trench;
removing the side spacers;
removing the sacrificial material from the at least one first trench;
removing the fill material from the at least one second trench; and
depositing a conductive material in the at least one first trench and the at least one second trench.

2. The method of claim 1 , wherein forming the plurality of backbone structures comprises:
depositing a backbone material on the first hardmask;
patterning spacers adjacent the backbone material; and
etching the backbone material to transfer the pattern of the spacers into the backbone material.

3. The method of claim 2 , wherein patterning spacers adjacent the backbone material comprises:
patterning sacrificial hardmask structures adjacent the backbone material;
depositing a conformal spacer material layer over the plurality of backbone structures;
anisotropically etching the conformal spacer material layer; and
removing the sacrificial hardmask structures.

4. The method of claim 1 , wherein forming side spacers adjacent sides of each of the plurality of backbone structures comprises:
depositing a conformal side spacer material layer over the plurality of backbone structures; and
anisotropically etching the conformal side spacer material layer.

5. The method of claim 1 , wherein removing the side spacers comprises polishing away the side spacers.

6. The method of claim 1 , wherein depositing the sacrificial material in the at least one first trench comprises depositing a material selected from the group consisting of titanium nitride, titanium oxide, ruthenium, and cobalt.

7. The method of claim 1 , wherein depositing the fill material in the at least one second trench comprises depositing a carbon hardmask in the at least one second trench.

8. The method of claim 1 , wherein forming the dielectric layer on the substrate comprises forming a low k dielectric layer.

9. The method of claim 1 , wherein forming the plurality of backbone structures on the first hardmask layer comprises forming the plurality of backbone structures from a material selected from the group consisting of polysilicon, amorphous silicon, amorphous carbon, silicon carbide, silicon nitride and germanium.

10. The method of claim 1 , wherein depositing the conductive material in the at least one first trench and the at least one second trench comprises depositing a metal.

11. A method of forming a microelectronic structure, comprising:
forming a dielectric layer on a substrate, wherein the substrate includes a first contact structure and a second contact structure;
forming a first hardmask layer on the dielectric layer;
forming a plurality of backbone structures on the first hardmask layer;
forming side spacers adjacent sides of each of the plurality of backbone structures;
etching a portion of the first hardmask layer and a portion of the dielectric layer between adjacent side spacers between at least two adjacent backbone structures to form at least one first trench, without removing any of the plurality of backbone structures;
forming a first via extending from the at least one first trench to the substrate first contact structure;
depositing a sacrificial material in the at least one first trench;
removing at least one backbone structure and etching a portion of the first hardmask layer and the dielectric layer which resided below the at least one backbone structure to form at least one second trench, without removing the sacrificial material in the at least one first trench;
forming a second via extending from the at least one second trench to the substrate second contact structure;
depositing a fill material in the at least one second trench;
removing the side spacers;
removing the sacrificial material from the at least one first trench;
removing the fill material from the at least one second trench; and
depositing a conductive material in the at least one first trench, the first via, the at least one second trench, and the second via.

12. The method of claim 11 , wherein forming the plurality of backbone structures comprises:
depositing a backbone material on the first hardmask;
patterning spacers adjacent the backbone material; and
etching the backbone material to transfer the pattern of the spacers into the backbone material.

13. The method of claim 12 , wherein patterning spacers adjacent the backbone material comprises:
patterning sacrificial hardmask structures adjacent the backbone material;
depositing a conformal spacer material layer over the plurality of backbone structures;
anisotropically etching the conformal spacer material layer; and
removing the sacrificial hardmask structures.

14. The method of claim 11 , wherein forming side spacers adjacent sides of each of the plurality of backbone structures comprises:
depositing a conformal side spacer material layer over the plurality of backbone structures; and
anisotropically etching the conformal side spacer material layer.

15. The method of claim 11 , wherein removing the side spacers comprises polishing away the side spacers.

16. The method of claim 11 , wherein depositing the sacrificial material in the at least one first trench comprises depositing a material selected from the group consisting of titanium nitride, titanium oxide, ruthenium, and cobalt.

17. The method of claim 11 , wherein depositing the fill material in the at least one second trench comprises depositing a carbon hardmask in the at least one second trench.

18. The method of claim 11 , wherein forming the dielectric layer on the substrate comprises forming a low k dielectric layer.

19. The method of claim 11 , wherein forming the plurality of backbone structures on the first hardmask layer comprises forming the plurality of backbone structures from a material selected from the group consisting of polysilicon, amorphous silicon, amorphous carbon, silicon carbide, silicon nitride and germanium.

20. The method of claim 11 , wherein depositing the conductive material in the at least one first trench and the at least one second trench comprises depositing a metal.

21. A method of forming a microelectronic structure, comprising:
forming a dielectric layer on a substrate, wherein the substrate includes a first contact structure and a second contact structure;
forming a hardmask layer on the dielectric layer;
forming a plurality of backbone structures on a hardmask layer;
forming side spacers adjacent sides of each of the plurality of backbone structures;
etching a porti

Assignees

• Intel Corp

Inventors

• Jezewski Christopher J
• Chawla Jasmeet S
• Singh Kanwal Jit
• Myers Alan M
• Tan Elliot N
• Schenker Richard E

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title