Computing system with direct invalidation in a hierarchical cache structure based on at least one designated key identification code

Patent metadata

Field	Value
Publication number	US-12086065-B2
Application number	US-202218046625-A
Country	US
Kind code	B2
Filing date	Oct 14, 2022
Priority date	Nov 19, 2021
Publication date	Sep 10, 2024
Grant date	Sep 10, 2024

Abstract

A computing system with a first instruction of an instruction set architecture (ISA) for direct invalidation, without writing back, in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for direct invalidation, without writing back, in the hierarchical cache structure based on a plurality of designated key identification codes is shown. A decoder transforms the first or second instruction into at least one microinstruction. Based on the at least one microinstruction, one direct invalidation request is provided corresponding to each designated key identification code, to be passed to the hierarchical cache structure through a memory ordering buffer. For each direct invalidation request, the cache line write-back and invalidation regarding a designated key identification code is performed on a last-level cache first, and then is performed on the in-core cache modules.

First claim

What is claimed is:

1. A computing system with direct invalidation in a hierarchical cache structure based on one single designated key identification code, comprising:
a first core provided by a first processor that is fabricated on a first die, including a decoder, a memory ordering buffer, and a first in-core cache module; and
a first last-level cache, fabricated in the first processor;
wherein:
in response to a first instruction of an instruction set architecture that is provided for direct invalidation in a hierarchical cache structure based on one single designated key identification code, the decoder outputs at least one microinstruction, wherein the direct invalidation is performed without writing back;
based on the at least one microinstruction, a direct invalidation request is provided to the first in-core cache module through the memory ordering buffer, and then passed to the first last-level cache by the first in-core cache module;
in response to the direct invalidation request, the first last-level cache searches itself to determine which cache lines within the first last-level cache match the designated key identification code, and invalidates all matched cache lines within the first last-level cache, without writing back the matched cache lines from the first last-level cache to a system memory; and
a first storage unit, storing the designated key identification code indicated by the first instruction;
wherein:
the direct invalidation request does not carry the designated key identification code;
in response to the direct invalidation request, the first last-level cache obtains the designated key identification code from the first storage unit, and searches itself according to the designated key identification code obtained from the first storage unit to determine which cache lines within the first last-level cache match the designated key identification code.

2. The computing system as claimed in claim 1 , wherein:
a cache line is invalidated by de-asserting a valid bit of the cache line.

3. The computing system as claimed in claim 1 , wherein:
the direct invalidation request carries the designated key identification code; and
the first last-level cache searches itself according to the designated key identification code carried on the direct invalidation request to determine which cache lines within the first last-level cache match the designated key identification code.

4. The computing system as claimed in claim 1 , wherein:
the first storage unit is designed in the first core for calculations of the first core, or is placed in an uncore area of the first processor to be shared by a plurality of cores of the first processor.

5. A computing system with direct invalidation in a hierarchical cache structure based on one single designated key identification code, comprising:
a first core provided by a first processor that is fabricated on a first die, including a decoder, a memory ordering buffer, and a first in-core cache module; and
a first last-level cache, fabricated in the first processor;
wherein:
in response to a first instruction of an instruction set architecture that is provided for direct invalidation in a hierarchical cache structure based on one single designated key identification code, the decoder outputs at least one microinstruction, wherein the direct invalidation is performed without writing back;
based on the at least one microinstruction, a direct invalidation request is provided to the first in-core cache module through the memory ordering buffer, and then passed to the first last-level cache by the first in-core cache module; and
in response to the direct invalidation request, the first last-level cache searches itself to determine which cache lines within the first last-level cache match the designated key identification code, and invalidates all matched cache lines within the first last-level cache, without writing back the matched cache lines from the first last-level cache to a system memory;
wherein:
the first processor further includes a first snoop filter;
corresponding to each matched cache line in the first last-level cache, the first last-level cache provides one snoop request to be passed to the first in-core cache module through the first snoop filter;
each snoop request carries a tag to represent the corresponding matched cache line, and the tag further tags associated cached contents in the other levels of the hierarchical cache structure;
in response to each snoop request, the first in-core cache module searches itself to determine which cache lines within the first in-core cache module match the tag carried on the snoop request, and invalidates all matched cache lines within the first in-core cache module, without writing back the matched cache lines from the first in-core cache module to the system memory.

6. The computing system as claimed in claim 5 , wherein:
the first in-core cache module includes a level 1 cache and a level 2 cache;
the first last-level cache is a level 3 cache;
the direct invalidation request is transferred from the level 1 cache to the level 2 cache, and then passed to the level 3 cache by the level 2 cache;
each snoop request from the first snoop filter is received by the level 2 cache, and then passed to the level 1 cache by the level 2 cache;
in response to each snoop request, the level 2 cache searches itself to determine which cache lines within the level 2 cache match the tag carried on the snoop request, and invalidates all matched cache lines within the level 2 cache, without writing back the matched cache lines from the level 2 cache to the system memory; and
in response to each snoop request, the level 1 cache searches itself to determine which cache lines within the level 1 cache match the tag carried on the snoop request, and invalidates all matched cache lines within the level 1 cache, without writing back the matched cache lines from the level 1 cache to the system memory.

7. The computing system as claimed in claim 5 , wherein:
the first processor further includes a second core, and the second core includes a second in-core cache module;
each snoop request is further transferred to the second in-core cache module through the first snoop filter;
in response to each snoop request, the second in-core cache module searches itself to determine which cache lines within the second in-core cache module match the tag carried on the snoop request, and invalidates all matched cache lines within the second in-core cache module, without writing back the matched cache lines from the second in-core cache module to the system memory.

8. The computing system as claimed in claim 7 , wherein:
the first core and the second core each include one level 1 cache to implement the first in-core cache module and the second in-core cache module;
the first processor includes a level 2 cache which is shared by the first core and the second core;
the first last-level cache is a level 3 cache;
the direct invalidation request is transferred from the level 1 cache of the first core to the level 2 cache shared by the first core and the second core, and then passed to the level 3 cache by the level 2 cache;
each snoop request from the first snoop filter is received by the level 2 cache shared by the first core and the second core, and then passed to the level 1 cache of the first core and the level 1 cache of the second core by the level 2 cache;
in response to each snoop request, the level 2 cache searches itself to determine which cache lines within the level 2 cache match the tag carried on the snoop request, and invalidates all matched cache lines within the level 2 cache, without writing back the matched cache lines from the level 2 cache to th

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Wang Weilin
• Guan Yingbing
• Yi Lei

Classifications

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F12/0891 Primary

  using clearing, invalidating or resetting means · CPC title