Electronic system comprising a control unit configured to communicate with a memory

US12086008B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12086008-B2
Application numberUS-202217942354-A
CountryUS
Kind codeB2
Filing dateSep 12, 2022
Priority dateSep 14, 2021
Publication dateSep 10, 2024
Grant dateSep 10, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the first power supply sector, the control unit includes a first configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the operating mode. In the second power supply sector, the control unit includes a second configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the low consumption mode.

First claim

Opening claim text (preview).

The invention claimed is: 1. A system, comprising: a control unit electrically connectable to an input of a memory via a communication interface; where the control unit includes two power supply sectors: a first power supply sector configured to be powered when the control unit is in an operating mode and to be switched off when the control unit is in a low consumption mode, and a second power supply sector configured to be powered when the control unit is in the operating mode and powered when the control unit is in the low consumption mode; wherein the control unit includes: in the first power supply sector, a first configuration circuit operating when the control unit is in the operating mode to configure a polarization value of said input of the memory via the communication interface; and in the second power supply sector, a second configuration circuit operating when the control unit is in the low consumption mode to configure the polarization value of said input of the memory via the communication interface. 2. The system according to claim 1 , further comprising selection circuitry configured to select said first configuration circuit to configure the polarization value of said input of the memory when the control unit is in the operating mode and select said second configuration circuit to configure the polarization value of said input of the memory when the control unit is in the low consumption mode. 3. The system according to claim 1 , wherein the first and second configuration circuit are configured to apply one of a high logic state or a low logic state to the input of the memory. 4. The system according to claim 3 , further comprising: a pull-up resistor configured to be connected to said communication interface for applying the high logic state to the input of the memory; a pull-down resistor configured to be connected to said communication interface for applying the low logic state to the input of the memory; switches connected in series with the pull-up resistor and pull-down resistor that are selectively controlled to activate or deactivate said pull-up resistor and said pull-down resistor according to the logic state to be applied to the input of the memory defined by said first and second configuration circuits. 5. The system according to claim 4 , wherein said pull-up resistor and said pull-down resistor are provided in an input/output port of the control unit configured to be connected to the input of the memory via said communication interface. 6. The system according to claim 4 , further comprising: the memory; and said communication interface connecting the memory to the control unit; wherein said pull-up resistor and said pull-down resistor are connected to the communication interface between the control unit and the memory. 7. The system according to claim 1 , wherein the first configuration circuit comprises a configuration register defining a configuration of the polarization value of the input of the memory when the control unit is in the operating mode, said configuration register being provided in an input/output port of the control unit configured to be connected to the input of the memory via said communication interface. 8. The system according to claim 1 , wherein the second configuration circuit comprise a configuration register defining a configuration of the polarization value of the input of the memory when the control unit is in the low consumption mode, said configuration register being provided in an input/output port of the control unit configured to be connected to the input of the memory via said communication interface. 9. The system according to claim 1 , wherein the polarization value of the input of the memory to be configured operates to activate or deactivate the memory, and wherein the second configuration circuit operates to configure this polarization value of the input of the memory to deactivate the memory when the control unit is in the low consumption mode. 10. A method for configuring a polarization value of an input of a memory by a control unit electrically connected to the input of the memory via a communication interface, wherein control unit has two power supply sectors: a first power supply sector configured to be powered when the control unit is in an operating mode and to be switched off when the control unit is in a low consumption mode, and a second power supply sector configured to be powered when the control unit is in the operating mode and powered when the control unit is in the low consumption mode, the method comprising: using a first configuration circuit of the control unit placed in the first power supply sector to configure the polarization value of the input of the memory via the communication interface when the control unit is in the operating mode; and using a second configuration circuit of the control unit placed in the second power supply sector to configure the polarization value of the input of the memory via the communication interface when the control unit is in the low consumption mode. 11. The method according to claim 10 , further comprising: selecting by selection circuits of said first configuration circuit to configure the polarization value of the input of the memory when the control unit is in the operating mode; and selecting by selection circuits of said second configuration circuit to configure the polarization value of the input of the memory when the control unit is in the low consumption mode. 12. The method according to claim 10 , further comprising applying by the first and second configuration circuit of one of a high logic state or a low logic state to the input of the memory. 13. The method according to claim 12 , wherein: applying the high logic state comprises using a pull-up resistor configured to be connected to said communication interface; applying the low logic state comprises using a pull-down resistor configured to be connected to said communication interface. 14. The method according to claim 13 , further comprising: selectively actuating a switch connected in series with said pull-up resistor according to the logic state to be applied to the input of the memory defined by one or more of the first and second configuration circuits to apply the high logic state; and selectively actuating a switch connected in series with said pull-down resistor according to the logic state to be applied to the input of the memory defined by one or more of the first and second configuration circuit to apply the low logic state. 15. The method according to claim 14 , wherein said pull-up resistor and said pull-down resistor are provided in an input/output port of the control unit configured to be connected to the input of the memory via said communication interface. 16. The method according to claim 14 , wherein said pull-up resistor and said pull-down resistor are connected to the communication interface between the control unit and the memory. 17. The method according to claim 10 , further comprising loading the polarization value of the input of the memory in a configuration register comprised in the first configuration circuit when the control unit is in the operating mode, said configuration register being provided in an input/output port of the control unit configured to be connected to the input of the memory via said communication interface. 18. The method according to claim 10 , loading the polarization value of the input of the memory in a configuration register comprised in the second configuration circuit when the control unit is i

Assignees

Inventors

Classifications

  • by means of a pull-up or down element · CPC title

  • by switching off individual functional units in the computer system · CPC title

  • Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

  • Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

  • G06F1/3225Primary

    of memory devices · CPC title

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What does patent US12086008B2 cover?
A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the f…
Who is the assignee on this patent?
St Microelectronics Rousset, St Microelectronics Des & Appl
What technology area does this patent fall under?
Primary CPC classification G06F1/3225. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 10 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).