Technique to lower switching power of bit-lines by adiabatic charging of sram memories

Patent metadata

Field	Value
Publication number	US-2020105321-A1
Application number	US-201816147454-A
Country	US
Kind code	A1
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

A system and method for efficiently managing switching power of bit lines. In various embodiments, a first bit line in a memory array is pre-charged in multiple discrete steps, rather than in one continuous step. For a read operation that completed and read a logic low level from a first storage node, the first bit line is pre-charged from a ground reference level to a first power supply voltage. Similarly, a second bit line corresponding to a second storage node storing an inverse voltage level of the first storage node is pre-charged from a larger second power supply voltage to the smaller first power supply voltage. When the first time interval has elapsed, the first and second bit lines are pre-charged from the first power supply voltage to the second power supply voltage during a second time interval. Discrete steps are also used for pre-charging after write operations.

First claim

1 . An apparatus comprising:
circuitry configured to:
receive, by bit line charging circuitry, a first power supply voltage;
receive, by each of a random access memory cell and the bit line charging circuitry, a second power supply voltage greater than the first power supply voltage;
in response to determining completion of an access operation that accesses a first storage node that stores a ground reference voltage level:
pre-charge, by the bit line charging circuitry, a first bit line corresponding to the first storage node to the first power supply voltage during a first time interval; and
in response to determining the first time interval has elapsed, pre-charge, by the bit line charging circuitry, the first bit line from the first power supply voltage to the second power supply voltage during a second time interval.

2 . The apparatus as recited in claim 1 , wherein the circuitry further comprises a second storage node configured to store a voltage level corresponding to a binary logical inverse of the voltage level stored on the first storage node, and wherein in response to determining the access operation is a read operation, the circuitry is configured to:
pre-charge a second bit line corresponding to the second storage node to the first power supply voltage during the first time interval; and in response to determining the first time interval has elapsed, pre-charge the second bit line from the first power supply voltage to the second power supply voltage during the second time interval.

3 . The apparatus as recited in claim 2 , wherein upon completion of the read operation, the first bit line stores a ground reference voltage level and the second bit line stores the second power supply voltage, or vice-versa.

4 . The apparatus as recited in claim 1 , wherein the circuitry further comprises a second storage node configured to store a voltage level corresponding to a binary logical inverse of the voltage level stored on the first storage node, and wherein in response to determining the access operation is a write operation, the circuitry is configured to determine from received write data that the first bit line discharged during the write operation.

5 . The apparatus as recited in claim 4 , wherein upon completion of the write operation, the circuitry is further configured to prevent pre-charging of the second bit line.

6 . The apparatus as recited in claim 4 , wherein the circuitry is further configured to:
receive a third power supply voltage less than the first power supply voltage; and in response to determining completion of the write operation, pre-charge the first bit line from the third power supply voltage to a ground reference voltage level during a third time interval prior to the first time interval.

7 . The apparatus as recited in claim 6 , wherein the third power supply voltage is a negative power supply voltage.

8 . The apparatus as recited in claim 1 , wherein the circuitry is further configured to:
enable a first device and disable a second device different from the first device when pre-charging the first bit line during the first time interval; and enable the second device and disable the first device when pre-charging the first bit line during the second time interval.

9 . A method, comprising:
receiving, by bit line charging circuitry, a first power supply voltage; receiving, by each of a random access memory cell and the bit line charging circuitry, a second power supply voltage greater than the first power supply voltage; in response to determining completion of an access operation that accesses a first storage node that stores a ground reference voltage level:
pre-charging, by the bit line charging circuitry, a first bit line corresponding to the first storage node to the first power supply voltage during a first time interval; and
in response to determining the first time interval has elapsed, pre-charging, by the bit line charging circuitry, the first bit line from the first power supply voltage to the second power supply voltage during a second time interval.

10 . The method as recited in claim 9 , further comprising:
storing on a second node a voltage level corresponding to a binary logical inverse of the voltage level stored on the first storage node; and in response to determining the access operation is a read operation:
pre-charging a second bit line corresponding to the second storage node to the first power supply voltage during the first time interval; and
in response to determining the first time interval has elapsed, pre-charging the second bit line from the first power supply voltage to the second power supply voltage during the second time interval.

11 . The method as recited in claim 10 , wherein upon completion of the read operation, the first bit line stores a ground reference voltage level and the second bit line stores the second power supply voltage, or vice-versa.

12 . The method as recited in claim 9 , further comprising:
storing on a second storage node a voltage level corresponding to a binary logical inverse of the voltage level stored on the first storage node; and in response to determining the access operation is a write operation, determining from received write data that the first bit line discharged during the write operation.

13 . The method as recited in claim 12 , wherein upon completion of the write operation, the method further comprises preventing pre-charging of the second bit line.

14 . The method as recited in claim 12 , further comprising:
receiving a third power supply voltage less than the first power supply voltage; and in response to determining completion of the write operation, pre-charging the first bit line from the third power supply voltage to a ground reference voltage level during a third time interval prior to the first time interval.

15 . The method as recited in claim 14 , wherein the third power supply voltage is a negative power supply voltage.

16 . The method as recited in claim 9 , further comprising:
enabling a first device and disable a second device different from the first device when pre-charging the first bit line during the first time interval; and enabling the second device and disable the first device when pre-charging the first bit line during the second time interval.

17 . A memory comprising:
an array comprising a plurality of storage nodes, each configured to store data; a plurality of row decoders, each configured to select a given memory line stored in the array based on a received request address, wherein each row decoder receives a first power supply voltage; a plurality of column decoders, each configured to select a given bit line of a plurality of bit lines in the one or more arrays based on the received request address, wherein each column decoder receives the first power supply voltage; wherein a first storage node in the array identified by each of a first row decoder and a first column decoder based on the received request address is configured to store a ground reference voltage level or a positive, non-zero voltage level using a second power supply voltage greater than the first power supply voltage; and logic; and in response to determining completion of an access operation that accesses the first storage node that stores a ground reference voltage level, the logic is configured to:
pre-charge a first bit line corresponding to the first storage node to the first power supply voltage during a first time interval; and
in response to determining the first time interval has elapsed, pre-charge t

Assignees

• Apple Inc

Inventors

• Sinangil Yildiz
• Abu-Rahma Mohamed H

Classifications

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title