Efficient fabrication of memory structures

Patent metadata

Field	Value
Publication number	US-12082425-B2
Application number	US-202318124438-A
Country	US
Kind code	B2
Filing date	Mar 21, 2023
Priority date	Jul 28, 2020
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

Methods, systems, and devices for efficient fabrication of memory structures are described. A multi-deck memory device may be fabricated using a sequence of fabrication steps that include depositing a first metal layer, depositing a cell layer on the first metal layer to form memory cells of the first memory deck, and depositing a second metal layer on the cell layer. The second metal layer may be deposited using a single deposition process rather than using multiple deposition processes. A second memory deck may be formed on the second metal layer such that stacked memory cells from the first and second deck share the use of the second metal layer. Using a single deposition process for the second metal layer may decrease the quantity of fabrication steps used to fabricate the multi-deck memory array and reduce or eliminate the exposure of the cell material to metal etchants.

First claim

What is claimed is:

1. An apparatus, comprising:
a first metal layer formed over a substrate based at least in part on a first deposition process, the first metal layer corresponding to a first access line associated with accessing a first memory cell;
the first memory cell formed over the first metal layer;
a second metal layer formed, using a single second deposition process, over the first memory cell, the second metal layer corresponding to a second access line associated with the first memory cell;
a second memory cell formed over the second metal layer;
a first sealant layer on a first portion of the first metal layer, a first portion of the first memory cell, a first portion of the second metal layer, and a first portion of the second memory cell; and
a second sealant layer on a second portion of the first metal layer, a second portion of the first memory cell, a second portion of the second metal layer, and a second portion of the second memory cell.

2. The apparatus of claim 1 , wherein the second access line is further associated with accessing the second memory cell.

3. The apparatus of claim 1 , wherein the single second deposition process comprises a deposition of a quantity of a metal material and excludes any additional quantity of the metal material deposited as part of another deposition process.

4. The apparatus of claim 1 , wherein a thickness of the first metal layer is less than a thickness of the second metal layer based at least in part on the single second deposition process.

5. The apparatus of claim 1 , wherein:
the first memory cell comprises a portion of a first electrode layer, a portion of a first cell storage layer, and a portion of a second electrode layer, and
the second memory cell comprises a portion of a third electrode layer, a portion of a second cell storage layer, and a portion of a fourth electrode layer.

6. The apparatus of claim 1 , further comprising:
a third metal layer formed over the second memory cell, the third metal layer corresponding to a third access line associated with accessing the second metal layer.

7. The apparatus of claim 1 , wherein the second metal layer is formed based at least in part on a first mask layer formed over the second metal layer, the first mask layer associated with a first etching process to remove a first portion of the first mask layer, a first portion of the second metal layer, and a first portion of a material forming the first memory cell.

8. The apparatus of claim 1 , wherein the first memory cell comprises a chalcogenide material for storing a state of the first memory cell.

9. The apparatus of claim 1 , wherein the first metal layer and the second metal layer comprise tungsten.

10. The apparatus of claim 1 , wherein the first access line comprises a word line or a bit line.

11. The apparatus of claim 1 , wherein the second access line comprises a word line or a bit line.

12. The apparatus of claim 1 , wherein the single second deposition process comprises a deposition of a quantity of a metal material of the second metal layer that is greater than 55 nanometers.

13. The apparatus of claim 12 , wherein a thickness of the first metal layer is less than 55 nanometers.

14. A memory device, comprising:
a plurality of pillars arranged in a three-dimensional cross-point architecture, each pillar comprising:
a first memory cell coupled with a first access line and with a second access line;
a second memory cell coupled with the second access line and with a third access line, wherein the second access line comprises a quantity of a metal material deposited during a single deposition process;
a first sealant layer on a first portion of the first access line, a first portion of the first memory cell, a first portion of the second access line, and a first portion of the second memory cell; and
a second sealant layer on a second portion of the first access line, a second portion of the first memory cell, a second portion of the second access line, and a second portion of the second memory cell.

15. The memory device of claim 14 , wherein the first access line, the second access line, and the third access line each correspond to one of a word line or a bit line.

16. The memory device of claim 14 , wherein the first access line comprises a second quantity of the metal material deposited during a second deposition process before the single deposition process.

17. The memory device of claim 14 , wherein a thickness of the first access line is less than a thickness of the second access line based at least in part on the single deposition process.

18. The memory device of claim 14 , wherein the first memory cell comprises a chalcogenide material for storing a state of the first memory cell, and the metal material comprises tungsten.

19. The memory device of claim 14 , wherein the single deposition process comprises depositing a quantity of the metal material that is greater than 55 nanometers.

Assignees

• Micron Technology Inc

Inventors

• Lee Don Koun
• Baker Kevin Lee
• Wei Lei

Classifications

• H10N70/882

  Compounds of sulfur, selenium or tellurium, e.g. chalcogenides · CPC title

• H10N70/841

  Electrodes · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/231

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title