Metal-oxide-semiconductor capacitor and circuit board including the same embedded therein

US12080809B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12080809-B2
Application numberUS-202217722465-A
CountryUS
Kind codeB2
Filing dateApr 18, 2022
Priority dateMay 3, 2021
Publication dateSep 3, 2024
Grant dateSep 3, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A metal-oxide-semiconductor (MOS) capacitor can include a substrate including a semiconductor material, an oxide layer formed on a surface of the substrate, a conductive layer formed over at least a portion of the oxide layer, a first terminal connected with the surface of the substrate, and a second terminal connected with the conductive layer. The oxide layer can be connected in series between the substrate and the conductive layer to form a capacitor between the first terminal and the second terminal. Each of the first terminal and the second terminal can be exposed along the surface of the substrate for surface mounting the capacitor. The MOS capacitor can exhibit excellent high frequency performance. For example, an insertion loss of the MOS capacitor can be greater than about −0.75 dB for frequencies ranging from about 5 GHz to about 40 GHz.

First claim

Opening claim text (preview).

What is claimed is: 1. A capacitor comprising: a substrate comprising a semiconductor material; an oxide layer formed on a surface of the substrate; a conductive layer formed over at least a portion of the oxide layer; a first terminal connected with the surface of the substrate; and a second terminal connected with the conductive layer, wherein the oxide layer is connected in series between the substrate and the conductive layer to form the capacitor between the first terminal and the second terminal; wherein: each of the first terminal and the second terminal are exposed along the surface of the substrate for surface mounting the capacitor, the first terminal being co-planar with the oxide layer; the first terminal is spaced apart from the second terminal in a Y-direction; the oxide layer has an edge aligned with an X-direction that is perpendicular to the Y-direction; the edge of the oxide layer defines an end of the oxide layer and is spaced apart from an end of substrate in the Y-direction such that the end of the oxide layer is spaced apart from the end of the substrate in the Y-direction; the first terminal is located between the edge of the oxide layer and the end of the substrate in the Y-direction; the substrate comprises a first end surface and a second end surface that are perpendicular to the surface of substrate and that are spaced apart from one another along the Y-direction; and the first terminal is disposed adjacent to the first end surface and the second terminal is disposed adjacent to the second end surface. 2. The capacitor of claim 1 , wherein the first terminal is connected with the surface of the substrate at a location that is spaced apart from the oxide layer along the surface of the substrate. 3. The capacitor of claim 1 , wherein: the oxide layer covers a first portion of the surface of the substrate that is distinct from a second portion of the surface of the substrate that is free of the oxide layer; and the first terminal is connected with the surface of the substrate within the second portion of the surface of the substrate. 4. The capacitor of claim 1 , wherein the first terminal comprises an electrically conductive material deposited as a thin-film layer directly on the surface of the substrate. 5. The capacitor of claim 1 , wherein the semiconductor material of the substrate comprises silicon. 6. The capacitor of claim 1 , wherein the oxide layer comprises silicon oxide. 7. The capacitor of claim 1 , wherein the capacitor exhibits an insertion loss at the second terminal and for an input signal applied to the first terminal, the insertion loss being greater than about −0.75 dB for frequencies ranging from about 5 GHz to about 40 GHz. 8. The capacitor of claim 1 , wherein the capacitor exhibits an insertion loss at the second terminal and for an input signal applied to the first terminal, the insertion loss being greater than about −2 dB for frequencies ranging from about 5 GHz to about 60 GHz. 9. A capacitor comprising: a substrate comprising a semiconductor material; an oxide layer formed on a surface of the substrate; a conductive layer formed over the oxide layer; the conductive layer contained within a perimeter of the oxide layer; a first terminal formed on the surface of the substrate, the first terminal co-planar with the oxide layer; and a second terminal connected with the oxide layer, wherein the oxide layer is connected in series between the substrate and the conductive layer to form the capacitor between the first terminal and the second terminal; wherein the capacitor exhibits an insertion loss at the second terminal and for an input signal applied to the first terminal, the insertion loss being greater than about −0.75 dB for frequencies ranging from about 5 GHz to about 40 GHZ, wherein the substrate comprises a first end surface and a second end surface that are perpendicular to the surface of substrate and that are spaced apart from one another along a Y-direction, and wherein the first terminal is disposed adjacent to the first end surface and the second terminal is disposed adjacent to the second end surface. 10. The capacitor of claim 9 , wherein the first terminal is connected with the surface of the substrate at a location that is spaced apart from the oxide layer along the surface of the substrate. 11. The capacitor of claim 9 , wherein: the first terminal is spaced apart from the second terminal in a Y-direction; the oxide layer has an edge aligned with an X-direction that is perpendicular to the Y-direction, the edge of the oxide layer being spaced apart from an end of substrate in the Y-direction; and the first terminal is located between the edge of the oxide layer and the end of the substrate in the Y-direction. 12. The capacitor of claim 9 , wherein: the oxide layer covers a first portion of the surface of the substrate that is distinct from a second portion of the surface of the substrate that is free of the oxide layer; and the first terminal is connected with the surface of the substrate within the second portion of the surface of the substrate. 13. The capacitor of claim 9 , wherein the first terminal comprises an electrically conductive material that directly contacts the surface of the substrate. 14. The capacitor of claim 9 , wherein the semiconductor material of the substrate comprises silicon. 15. The capacitor of claim 9 , wherein the oxide layer comprises silicon oxide. 16. The capacitor of claim 9 , wherein the capacitor exhibits an insertion loss at the second terminal and for an input signal applied to the first terminal, the insertion loss being greater than about −2 dB for frequencies ranging from about 5 GHz to about 60 GHz. 17. A method of forming a capacitor comprising: forming an oxide layer on a surface of a substrate comprising a semiconductor material; depositing a conductive layer over the oxide layer such that the conductive layer is contained within a perimeter of the oxide layer; depositing a first terminal on the surface of the substrate such that the first terminal is co-planar with the oxide layer and is exposed along the surface of the substrate for surface mounting the capacitor; and depositing a second terminal on the conductive layer such that the second terminal is exposed along the surface of the substrate for surface mounting the capacitor, wherein the substrate comprises a first end surface and a second end surface that are perpendicular to the surface of substrate and that are spaced apart from one another along a Y-direction, and wherein the first terminal is disposed adjacent to the first end surface and the second terminal is disposed adjacent to the second end surface. 18. The method of claim 17 , wherein forming the oxide layer on the surface of the substrate comprises forming the oxide layer within a first portion of the surface of the substrate that is distinct from a second portion of the surface of the substrate that is free of the oxide layer; and depositing the first terminal comprises depositing the first terminal within the second portion of the surface of the substrate. 19. A circuit board comprising: a circuit board substrate having a mounting surface; a capacitor at least partially embedded within the circuit board substrate, the capacitor comprising: a substrate comprising a semiconductor material; an oxide layer formed on a surface of the substrate; a conductive layer formed over at least a portion of the oxide layer; a first terminal connected with the surf

Assignees

Inventors

Classifications

  • of conductor-insulator-semiconductor capacitors, e.g. trench capacitors · CPC title

  • H10D1/66Primary

    Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors · CPC title

  • Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)} · CPC title

  • Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations · CPC title

  • Form of non-self-supporting electrodes · CPC title

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What does patent US12080809B2 cover?
A metal-oxide-semiconductor (MOS) capacitor can include a substrate including a semiconductor material, an oxide layer formed on a surface of the substrate, a conductive layer formed over at least a portion of the oxide layer, a first terminal connected with the surface of the substrate, and a second terminal connected with the conductive layer. The oxide layer can be connected in series betwee…
Who is the assignee on this patent?
Kyocera Avx Components Corp
What technology area does this patent fall under?
Primary CPC classification H10D1/66. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 03 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).