Capacitor with limited substrate capacitance

Patent metadata

Field	Value
Publication number	US-11101072-B2
Application number	US-201816221789-A
Country	US
Kind code	B2
Filing date	Dec 17, 2018
Priority date	Jun 28, 2016
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

A capacitor that prevents generation of a substrate capacitance composed of an upper electrode, a substrate, and a lower electrode. Specifically, the capacitor includes a substrate; a lower electrode disposed on the substrate; a dielectric film disposed on the lower electrode; an upper electrode disposed on a part of the dielectric film; and a first terminal electrode that is connected to the upper electrode. Moreover, the upper electrode and the first terminal electrode are formed in a region for forming the lower electrode in a plan view of the capacitor viewed from the first terminal electrode side.

First claim

The invention claimed is:

1. A capacitor comprising:
a substrate;
an insulating layer disposed on an entire surface of the substrate;
a lower electrode having a planar shape and disposed on a planar surface of the insulating layer and above the substrate, with the lower electrode not extending an entire surface of the insulating;
a dielectric film disposed on at least a portion of the lower electrode and covering a peripheral edge of the lower electrode and a side extending therefrom to the insulating layer, such that the dielectric film covers the lower electrode and is disposed directly on a portion of the insulating layer that is not covered by the lower electrode;
an upper electrode disposed on a portion of the dielectric film;
a first terminal electrode disposed above the upper electrode and coupled thereto;
a protective layer disposed on a portion of the dielectric film and covering a peripheral edge of the dielectric film; and
a second terminal electrode coupled to the lower electrode and that extends outside the capacitor to be externally exposed, with the second terminal electrode including a single and continuous electrode that extends directly from the lower electrode to be externally exposed outside the capacitor,
wherein the upper electrode and the first terminal electrode are disposed in a region where the lower electrode is formed in a plan view of the capacitor relative to the first terminal electrode,
wherein the protective layer comprises a plurality of cavities with the first terminal electrode extending in a first cavity of the protective layer and the second terminal electrode extending in a second cavity of the protective layer, and
wherein each of the first and second terminal electrodes are arranged on an upper surface of the protective layer and in the first and second cavities, respectively.

2. The capacitor according to claim 1 , wherein the second terminal electrode is disposed in the region where the lower electrode is formed in the plan view of the capacitor relative to the first terminal electrode.

3. The capacitor according to claim 2 , wherein the dielectric film comprises a cavity with the second terminal electrode disposed therein and directly coupled to the lower electrode.

4. The capacitor according to claim 1 , wherein the upper electrode is disposed in a region where the first terminal electrode is formed in a plan view of the capacitor relative to the first terminal electrode.

5. The capacitor according to claim 1 , wherein the upper electrode and the first terminal electrode are disposed in a region within the peripheral edge of the lower electrode in the plan view of the capacitor relative to the first terminal electrode.

6. The capacitor according to claim 5 , wherein the upper electrode and the first terminal electrode are disposed in a position relative to the lower electrode, such that electric force from the upper electrode and the first terminal electrode pass through the dielectric film and into the lower electrode when a voltage is applied to the first terminal electrode, and the upper and lower electrodes are not capacitively coupled across the substrate.

7. The capacitor according to claim 1 , wherein the protective layer comprises a thickness that is at least 1 μm in a thickness direction of the capacitor that extends orthogonally to the surface of the substrate.

8. The capacitor according to claim 1 , wherein the upper electrode is disposed within a region of the first terminal in the plan view of the capacitor.

9. A capacitor comprising:
a substrate;
a lower electrode having a planar shape and disposed on a planar surface of the substrate and having an outer perimeter;
a dielectric film disposed on at least a portion of the lower electrode and covering the outer perimeter of the lower electrode and a side extending therefrom toward the substrate, such that the dielectric layer is disposed above a portion of the substrate without the lower electrode being disposed therebetween;
an upper electrode disposed on a portion of the dielectric film and in a region within the outer perimeter of the lower electrode relative to a plan view of the substrate;
a first terminal electrode disposed above the upper electrode and coupled thereto, with the first terminal electrode disposed in the region within the outer perimeter of the lower electrode relative to the plan view of the substrate;
a second terminal electrode coupled to the lower electrode and that extends outside the capacitor to be externally exposed, with the second terminal electrode including a single and continuous electrode that extends directly from the lower electrode to be externally exposed outside the capacitor; and
a protective layer disposed on a portion of the dielectric film and covering a peripheral edge of the dielectric film,
wherein the protective layer comprises a plurality of cavities with the first terminal electrode extending in a first cavity of the protective layer and the second terminal electrode extending in a second cavity of the protective layer, and
wherein each of the first and second terminal electrodes are arranged on an upper surface of the protective layer and in the first and second cavities, respectively.

10. The capacitor according to claim 9 , wherein the second terminal electrode is disposed in a region within the outer perimeter of the lower electrode relative to the plan view of the substrate, and wherein the dielectric film comprises a cavity with the second terminal electrode disposed therein and directly coupled to the lower electrode.

11. The capacitor according to claim 9 , further comprising an insulating film disposed between the substrate and the lower electrode.

12. The capacitor according to claim 11 , wherein the insulating layer is disposed on an entire surface of the substrate and between the substrate and the lower electrode, with the dielectric film being disposed on a portion of the insulating layer that is not covered by the lower electrode.

13. The capacitor according to claim 9 , wherein the upper electrode and the first terminal electrode are disposed in a position relative to the lower electrode, such that electric force from the upper electrode and the first terminal electrode pass through the dielectric film and into the lower electrode when a voltage is applied to the first terminal electrode, and the upper and lower electrodes are not capacitively coupled across the substrate.

14. The capacitor according to claim 9 , wherein the protective layer comprises a thickness that is at least 1 μm in a thickness direction of the capacitor that extends orthogonally to the surface of the substrate.

Assignees

• Murata Manufacturing Co

Inventors

• Harada Masatomi
• Izumitani Junko
• Kagawa Takeshi
• Ishida Nobuhiro

Classifications

• H10D86/85

  characterised by only passive components · CPC title

• H01G4/33 Primary

  Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)} · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D1/716

  having vertical extensions · CPC title