Display device using semiconductor light-emitting elements and manufacturing method therefor

Patent metadata

Field	Value
Publication number	US-12080689-B2
Application number	US-201917632058-A
Country	US
Kind code	B2
Filing date	Sep 3, 2019
Priority date	Aug 23, 2019
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

The present invention relates to a display device having a structure in which an assembly substrate on which self-assembly has taken place can be used as a final substrate, and a method for manufacturing same. According to an embodiment of the present invention, first-conductive-type electrodes of vertical-type semiconductor light-emitting elements can be connected to seed metal, which is used as a wiring electrode, via a solder part, and thus there is the effect of directly using, as a final substrate, an assembly substrate on which the vertical-type semiconductor light-emitting elements are self-assembled, without an additional transfer process.

First claim

What is claimed is:

1. A display device comprising:
a base portion;
a plurality of assembly electrodes extending along a first direction and formed at predetermined intervals on the base portion;
a first dielectric layer disposed on the base portion to cover the assembly electrodes;
a plurality of seed metals formed on the first dielectric layer and extending along the first direction;
a plurality of barrier ribs formed to cover at least a portion of a top of each of the plurality of seed metals, wherein a plurality of cells are formed on the first dielectric layer at predetermined intervals between the plurality of barrier ribs and wherein each cell overlaps at least a portion of a corresponding assembly electrode of the plurality of assembly electrodes;
a plurality of semiconductor light emitting diodes correspondingly positioned in the plurality of cells; and
a plurality of solder portions each positioned at at least a portion of a bottom surface of a corresponding cell to connect a corresponding semiconductor light emitting diode to a corresponding seed metal.

2. The display device of claim 1 , wherein each semiconductor light emitting diode comprises:
a first conductive electrode;
a first conductive semiconductor layer formed on the first conductive electrode;
an active layer formed on the first conductive semiconductor layer;
a second conductive semiconductor layer formed on the active layer; and
a second conductive electrode formed on the second conductive semiconductor layer,
wherein a corresponding solder portion is connected to the first conductive electrode.

3. The display device of claim 1 , further comprising a plurality of first electrodes each configured to connect first conductive electrodes of a corresponding subset of semiconductor light emitting diodes arranged along the first direction.

4. The display device of claim 3 , further comprising a plurality of electrode holes formed to pass through the first dielectric layer and the base portion, wherein each electrode hole is configured to allow a conductive material to pass therethrough to connect a corresponding solder portion and a corresponding first electrode.

5. The display device of claim 1 , further comprising a plurality of second electrodes each extending along a second direction perpendicular to the first direction and configured to connect second conductive electrodes of a corresponding subset of the semiconductor light emitting diodes arranged along the second direction.

6. A method for manufacturing a display device, the method comprising:
forming a plurality assembly electrodes extending along a first direction and formed at predetermined intervals on a base portion;
forming a first dielectric layer on the base portion to cover the assembly electrodes;
forming a plurality of seed metals on the first dielectric layer each extending along the first direction;
forming a plurality of barrier ribs to cover at least a portion of a top of each of the plurality of seed metals, wherein a plurality of cells are formed on the first dielectric layer at predetermined intervals between the plurality of barrier ribs and wherein each cell overlaps at least a portion of a corresponding assembly electrode of the plurality of assembly electrodes;
forming a metal plating layer on an exposed surface of each of the plurality of seed metals by applying a voltage to each of the plurality of seed metals;
seating a semiconductor light emitting diode in each of the plurality of cells; and
forming a solder portion to connect the semiconductor light emitting diode by heating the corresponding seed metal and metal plating layer.

7. The method of claim 6 , wherein each semiconductor light emitting diode comprises:
a first conductive electrode;
a first conductive semiconductor layer formed on the first conductive electrode;
an active layer formed on the first conductive semiconductor layer;
a second conductive semiconductor layer formed on the active layer; and
a second conductive electrode formed on the second conductive semiconductor layer,
wherein a corresponding solder portion is connected to the first conductive electrode.

8. The method of claim 6 , wherein forming the solder portion comprises an annealing process.

9. The method of claim 6 , further comprising:
forming a plurality of first electrodes each configured to connect first conductive electrodes of a corresponding subset of semiconductor light emitting diodes arranged along the first direction.

10. The method of claim 9 , further comprising:
forming a plurality of electrode holes through the first dielectric layer and the base portion, wherein each electrode hole is configured to allow a conductive material to pass therethrough to connect a corresponding solder portion and a corresponding first electrode.

11. The method of claim 6 , further comprising:
forming a plurality of second electrodes each extending along a second direction perpendicular to the first direction and configured to connect second conductive electrodes of a corresponding subset of the semiconductor light emitting diodes arranged along the second direction.

12. The method of claim 6 , wherein seating the semiconductor light emitting diodes comprises applying an electric field and a magnetic field to the semiconductor light emitting diodes disposed in a fluid.

Assignees

• Lg Electronics Inc

Inventors

• Kim Dohee
• Kim Gunho
• Shin Yongil
• Shim Bongchu
• Cho Hyunwoo

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07336

  Soldering or alloying · CPC title

• H10W72/342

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title