Layered bonding material, semiconductor package, and power module

Patent metadata

Field	Value
Publication number	US-12080671-B2
Application number	US-202218288636-A
Country	US
Kind code	B2
Filing date	Apr 18, 2022
Priority date	Apr 28, 2021
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

A layered bonding material 10 includes a base material 11 , a first solder section 12 a stacked on a first surface of the base material 11 , and a second solder section 12 b stacked on a second surface of the base material 11 . A coefficient of linear expansion of the base material 11 is 5.5 to 15.5 ppm/K, the first solder section 12 a and the second solder section 12 b are made of lead-free solder, and both of a thickness of the first solder section 12 a and a thickness of the second solder section 12 b are 0.05 to 1.0 mm.

First claim

The invention claimed is:

1. A layered bonding material comprising:
a base material;
a first solder section stacked on a first surface of the base material; and
a second solder section stacked on a second surface of the base material, wherein
a coefficient of linear expansion of the base material is 5.5 to 15.5 ppm/K,
the first solder section and the second solder section are made of lead-free solder, and
both of a thickness of the first solder section and a thickness of the second solder section are 0.05 to 1.0 mm.

2. The layered bonding material according to claim 1 , wherein the lead-free solder has a Young's modulus of 45 GPa or higher and tensile strength of 100 MPa or lower.

3. The layered bonding material according to claim 2 , wherein the Young's modulus of the lead-free solder is 55 GPa or higher.

4. The layered bonding material according to claim 1 , wherein the base material has a mesh shape with a lattice interval of 2.0 mm or larger.

5. The layered bonding material according to claim 1 , wherein the coefficient of linear expansion of the base material is 5.9 to 14.4 ppm/K.

6. The layered bonding material according to claim 5 , wherein the coefficient of linear expansion of the base material is 7.0 to 11.6 ppm/K.

7. The layered bonding material according to claim 3 , wherein the coefficient of linear expansion of the base material is 7.7 to 9.9 ppm/K.

8. The layered bonding material according to claim 1 , wherein the base material is made of any one of a Cu—W-based material, a Cu—Mo-based material, a layered material of the Cu—W-based material and the Cu—Mo-based material, a composite material obtained by stacking a Cu-based material on both of a first surface and a second surface of the Cu—W-based material, a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the Cu—Mo-based material, and a composite material obtained by stacking the Cu-based material on both of a first surface and a second surface of the layered material of the Cu—W-based material and the Cu—Mo-based material.

9. The layered bonding material according to claim 1 , wherein a Cu content of the base material is 60% or lower.

10. The layered bonding material according to claim 1 , wherein a Cu content of the base material is 15% or higher.

11. The layered bonding material according to claim 1 , wherein an interface between at least one of the first solder section and the second solder section and the base material is undercoated with Ni and Sn in order from the base material side.

12. The layered bonding material according to claim 1 , wherein at least one of a ratio of thicknesses of the base material and the first solder section and a ratio of thicknesses of the base material and the second solder section is 2:1 to 10:1.

13. The layered bonding material according to claim 1 , wherein a melting point of the lead-free solder is 210° C. or higher.

14. The layered bonding material according to claim 1 , wherein a melting point of the lead-free solder is 230° C. or higher.

15. A semiconductor package comprising:
a substrate;
a semiconductor device disposed on the substrate; and
a layered bonding material disposed between the substrate and the semiconductor device and bonding the substrate and the semiconductor device, wherein
the layered bonding material includes:
a base material;
a first solder section stacked on a first surface of the base material; and
a second solder section stacked on a second surface of the base material,
a coefficient of linear expansion of the base material is 5.5 to 15.5 ppm/K,
the first solder section and the second solder section are made of lead-free solder, and
both of a thickness of the first solder section and a thickness of the second solder section are 0.05 to 1.0 mm.

16. A semiconductor package comprising:
a substrate;
a semiconductor device disposed on the substrate;
a first layered bonding material disposed between the substrate and the semiconductor device and bonding the substrate and the semiconductor device;
a heat radiating section disposed on an opposite side of the semiconductor device on the substrate; and
a second layered bonding material disposed between the substrate and the heat radiating section and bonding the substrate and the heat radiating section, wherein
at least one of the first layered bonding material and the second layered bonding material includes:
a base material;
a first solder section stacked on a first surface of the base material; and
a second solder section stacked on a second surface of the base material,
a coefficient of linear expansion of the base material is 5.5 to 15.5 ppm/K,
the first solder section and the second solder section are made of lead-free solder, and
both of a thickness of the first solder section and a thickness of the second solder section are 0.05 to 1.0 mm.

17. A power module comprising:
a substrate;
a power semiconductor device disposed on the substrate; and
a layered bonding material disposed between the substrate and the power semiconductor device and bonding the substrate and the power semiconductor device, wherein
the layered bonding material includes:
a base material;
a first solder section stacked on a first surface of the base material; and
a second solder section stacked on a second surface of the base material,
a coefficient of linear expansion of the base material is 5.5 to 15.5 ppm/K,
the first solder section and the second solder section are made of lead-free solder, and
both of a thickness of the first solder section and a thickness of the second solder section are 0.05 to 1.0 mm.

18. A power module comprising:
a substrate;
a power semiconductor device disposed on the substrate;
a first layered bonding material disposed between the substrate and the power semiconductor device and bonding the substrate and the power semiconductor device;
a heat radiating section disposed on an opposite side of the power semiconductor device on the substrate; and
a second layered bonding material disposed between the substrate and the heat radiating section and bonding the substrate and the heat radiating section, wherein
at least one of the first layered bonding material and the second layered bonding material includes:
a base material;
a first solder section stacked on a first surface of the base material; and
a second solder section stacked on a second surface of the base material,
a coefficient of linear expansion of the base material is 5.5 to 15.5 ppm/K,
the first solder section and the second solder section are made of lead-free solder, and
both of a thickness of the first solder section and a thickness of the second solder section are 0.05 to 1.0 mm.

Assignees

• Senju Metal Industry Co

Inventors

• Kameda Naoto
• DEI Kanta
• Tsuchiya Masato

Classifications

• H10W40/10

  Arrangements for heating · CPC title

• B32B15/01 Primary

  all layers being exclusively metallic {(making layered metal workpieces by pressure cladding B23K20/22; making coatings with a metallic material characterised by its composition C23C30/00)} · CPC title

• H10W72/30 Primary

  Die-attach connectors · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/352

  comprising metals or metalloids, e.g. solders · CPC title