Integrated circuit device with antenna effect protection circuit and method of manufacturing

Patent metadata

Field	Value
Publication number	US-12080658-B2
Application number	US-202117522376-A
Country	US
Kind code	B2
Filing date	Nov 9, 2021
Priority date	Sep 18, 2021
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

An integrated circuit (IC) device includes a first substrate, a through substrate via (TSV) in the first substrate, and a first antenna effect protection circuit over the first substrate and electrically coupled to the TSV. The first antenna effect protection circuit includes at least one first transistor of a first type, and at least one second transistor of a second type different from the first type. A gate terminal, a first terminal and a second terminal of each of the at least one first transistor and the at least one second transistor are electrically coupled together, and to the TSV.

First claim

What is claimed is:

1. An integrated circuit (IC) device, comprising:
a first substrate;
a through substrate via (TSV) in the first substrate; and
a first antenna effect protection circuit over the first substrate and electrically coupled to the TSV,
wherein
the first antenna effect protection circuit comprises at least one first transistor of a first type, and at least one second transistor of a second type different from the first type, and
a gate terminal, a first terminal and a second terminal of each of the at least one first transistor and the at least one second transistor are electrically coupled together, and to the TSV.

2. The IC device of claim 1 , wherein
the at least one first transistor comprises multiple first transistors,
the at least one second transistor comprises multiple second transistors, and
in the first antenna effect protection circuit, a number of the first transistors is greater than a number of the second transistors.

3. The IC device of claim 2 , wherein
the first transistors are N-type transistors, and
the second transistors are P-type transistors.

4. The IC device of claim 2 , wherein
the first transistors are P-type transistors, and
the second transistors are N-type transistors.

5. The IC device of claim 1 , further comprising:
a second substrate, wherein the first and second substrates are stacked one over another and bonded together; and
a second antenna effect protection circuit over the second substrate, wherein the first and second antenna effect protection circuits are electrically coupled correspondingly to first and second ends of the TSV.

6. The IC device of claim 5 , wherein
the second antenna effect protection circuit comprises at least one third transistor of the first type, and at least one fourth transistor of the second type, and
a gate terminal, a first terminal and a second terminal of each of the at least one third transistor and the at least one fourth transistor are electrically coupled together, and to the second end of the TSV.

7. An integrated circuit (IC) device, comprising:
a plurality of active regions extending along a first axis; and
a plurality of gate regions extending along a second axis transverse to the first axis,
wherein
the plurality of active regions and the plurality of gate regions are configured as a plurality of transistors,
gates, sources and drains of the plurality of transistors are electrically coupled together,
the plurality of active regions comprises:
a first active region of a first semiconductor type, and
second and third active regions of a second semiconductor type different from the first semiconductor type, and

the second and third active regions are spaced from each other along the second axis, and overlap the first active region along the first axis.

8. The IC device of claim 7 , wherein
the plurality of transistors comprises:
first transistors of a first type over the first active region, and
second transistors of a second type over the second and third active regions, the second type different from the first type.

9. The IC device of claim 7 , wherein
the third active region comprises discrete portions spaced from each other along the first axis, and
at least one of the discrete portions of the third active region is configured to receive a reference voltage.

10. The IC device of claim 7 , wherein
the plurality of active regions further comprises fourth and fifth active regions of the first semiconductor type,
along the second axis, the first through third active regions are arranged between the fourth and fifth active regions, and
each of the fourth and fifth active regions extends continuously along the first axis and overlaps, along the second axis, the first through third active regions.

11. The IC device of claim 7 , wherein
the plurality of active regions further comprises fourth and fifth active regions of the second semiconductor type,
the fourth and fifth active regions are spaced from each other along the second axis, and overlap the first active region along the first axis, and
along the first axis, the second and third active regions are on one side of the first active region, and the fourth and fifth active regions are on an opposite side of the first active region.

12. The IC device of claim 11 , wherein
the plurality of active regions further comprises sixth and seventh active regions of the first semiconductor type,
along the second axis, the first through fifth active regions are arranged between the sixth and seventh active regions, and
each of the sixth and seventh active regions extends continuously along the first axis and overlaps, along the second axis, the first through fifth active regions.

13. The IC device of claim 12 , further comprising:
an H-shaped or I-shaped doped well region over which the first, sixth and seventh active regions are arranged.

14. The IC device of claim 7 , wherein
the plurality of active regions further comprises fourth and fifth active regions of the first semiconductor type,
the fourth and fifth active regions are spaced from each other along the second axis,
the fourth and fifth active regions are spaced from and overlap the second and third active regions along the second axis, and
along the second axis, the fourth and fifth active regions overlap
the first active region, or
a sixth active region among the plurality of active regions, wherein the sixth active region is spaced from and overlaps the first active region along the second axis.

15. The IC device of claim 14 , wherein
the plurality of active regions further comprises a seventh active region of the first semiconductor type, and an eighth active region of the second semiconductor type,
along the second axis, the first through fifth active regions are arranged between the seventh and eighth active regions, and
each of the seventh and eighth active regions extends continuously along the first axis and overlaps, along the second axis, the first through fifth active regions.

16. The IC device of claim 14 , wherein
the plurality of active regions further comprises seventh and eighth active regions of the second semiconductor type,
the seventh and eighth active regions are spaced from each other along the second axis,
the seventh and eighth active regions are spaced from and overlap the second through fifth active regions along the second axis, and
along the second axis, the seventh and eighth active regions overlap
the first active region, or
the sixth active region, or
a ninth active region wherein the ninth active region is spaced from and overlaps the first active region along the second axis.

17. The IC device of claim 16 , wherein
the plurality of active regions further comprises tenth and eleventh active regions of the first semiconductor type,
along the second axis, the first through fifth, seventh and eighth active regions are arranged between the tenth and eleventh active regions, and
each of the tenth and eleventh active regions extends continuously along the first axis and overlaps, along the second axis, the first through fifth, seventh and eighth active regions.

18. A method of manufacturing an integrated circuit (IC) device, the method comprising:
forming, over a first substrate, first and second active regions extending along a first axis;
depositing and patterning, over the first and second active regions, first and second gate regions extending along a second axis transverse to the first axis, wherein
the first active region and the

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Tsmc China Company Ltd

Inventors

• Chen Cuncun
• Wang Xinyong
• Ma Yaqi
• Pan Lei
• Wang Mingjian
• Zhong Jialiang

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W42/60 Primary

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title