Efficient dual-path floating-point arithmetic operators

Patent metadata

Field	Value
Publication number	US-12079590-B2
Application number	US-202017133933-A
Country	US
Kind code	B2
Filing date	Dec 24, 2020
Priority date	Dec 24, 2020
Publication date	Sep 3, 2024
Grant date	Sep 3, 2024

Abstract

Systems and methods related to performing arithmetic operations on floating-point numbers. Floating-point arithmetic circuitry is configured to receive two floating-point numbers. The floating-point arithmetic circuitry includes a first path configured to perform a first operation on the two floating-point numbers based at least in part on a difference in size between the two floating-point numbers. The floating-point arithmetic circuitry includes a second path configured to perform a second operation on the two floating-point numbers based at least in part on the difference is size between the two floating-point numbers. The first path and the second path diverge from each other after receipt of the floating-point numbers in the floating-point arithmetic circuitry and converge on a shared adder that is used for the first operation and the second operation.

First claim

What is claimed is:

1. A system comprising:
floating-point arithmetic circuitry that receives two floating-point numbers, wherein the floating-point arithmetic circuitry comprises:
a first path that performs a first operation on the two floating-point numbers based at least in part on a difference in size between the two floating-point numbers; and
a second path that performs a second operation on the two floating-point numbers based at least in part on the difference in size between the two floating-point numbers, wherein the first path and the second path diverge from each other to converge on a shared adder that is used for the first operation and the second operation before the first and second paths diverge again; and
a multiplexer that selects between transmitting a first shifted mantissa from the first path to the shared adder and transmitting a second shifted mantissa from the second path to the shared adder.

2. The system of claim 1 , comprising a comparator that determines an exponent difference between exponents of the two floating-point numbers, wherein the first path performs the second operation on the two floating-point numbers when the exponent difference is less than a threshold.

3. The system of claim 2 , wherein the first operation comprises a subtraction when the exponent difference is greater than or equal to the threshold.

4. The system of claim 2 , wherein the first operation comprises an addition when the exponent difference is greater than or equal to the threshold.

5. The system of claim 2 , wherein the first operation comprises an addition when the exponent difference is less than the threshold.

6. The system of claim 2 , wherein the second operation comprises a subtraction when the exponent difference is less than the threshold.

7. The system of claim 2 , wherein the threshold comprises two.

8. The system of claim 1 , wherein the first path comprises a multi-bit shifter that generates the first shifted mantissa.

9. The system of claim 1 , wherein the second path comprises a single-bit shifter that generates the second shifted mantissa.

10. The system of claim 1 , wherein the second path comprises:
count leading zeros circuitry that receive a result from the shared adder and count a number of leading zeros in the result; and
a normalization shifter that shift the result to generate a normalized output based at least in part on the number of leading zeros.

11. The system of claim 1 , wherein the second path comprises a combination circuit that performs a shift detection and applies a shift by combining input bits from a result from the shared adder using a plurality of levels combining the input bits according to a logarithmic structure.

12. The system of claim 1 , wherein the first path comprises round and add circuitry that receives a result from the shared adder and to round the result.

13. The system of claim 12 , wherein the round and add circuitry comprises:
a parallel prefix circuit that receives the result;
a multiplexer that controls rounding at a rounding bit of the parallel prefix circuit;
an OR gate that drives a propagate bit of the parallel prefix circuit high based on a location of the rounding bit; and
an output multiplexer that shifts an output of the parallel prefix circuit left or right by one bit.

14. A method comprising:
receiving a first floating-point number;
receiving a second floating-point number;
splitting a first mantissa of the first floating-point number into a first path and a second path;
shifting the first mantissa in a first shifter in the first path to generate a first shifted mantissa;
shifting the first mantissa in a second shifter in the second path to generate a second shifted mantissa, wherein the first shifter is larger than the second shifter;
selecting a selected mantissa from the first shifted mantissa and the second shifted mantissa;
adding the selected mantissa to or subtracting the selected mantissa from a second mantissa of the second floating-point number in an adder/subtractor;
transmitting a result from the adder/subtractor into a third path and a fourth path; and
selecting an output between the third path and the fourth path.

15. The method of claim 14 , wherein the first floating-point number has a smaller exponent than the second floating-point number.

16. The method of claim 14 comprising determining how far to shift for normalization and normalizing the result in the third path.

17. The method of claim 14 comprising rounding the result in rounding circuitry in the fourth path, wherein the rounding circuitry comprises a single-bit shift configured to normalize the result after rounding the result.

18. A system comprising:
a first input configured to receive a first mantissa for a first floating-point number;
a second input configured to receive a second mantissa for a second floating-point number;
a first path having a first shifter configured to shift the first mantissa as a first shifted mantissa;
a second path having a second shifter configured to shift the first mantissa as a second shifted mantissa, wherein the second shifter is smaller than the first shifter, and the second shifter comprises a single-bit shifter;
a multiplexer configured to select between the first shifted mantissa and the second shifted mantissa and output a selected mantissa;
an adder/subtractor configured to receive the selected mantissa from the adder/subtractor;
a third path configured to determine how far to shift a result from the adder/subtractor based on values of bits in the result and to perform the shift;
a fourth path configured to round the result from the adder/subtractor; and
an output multiplexer configured to select an output for the system from the result in the third path and the result in the fourth path.

19. The system of claim 18 , wherein the third path comprises a combined circuit configured to perform the shift and determination using a logic tree structure configured to combine inputs in the result in a plurality of levels to generate output bits.

Assignees

• Intel Corp

Inventors

• Langhammer Martin
• Drane Theo

Classifications

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G06F5/012 Primary

  in floating-point computations · CPC title

• G06F7/49947

  Rounding · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title