Semiconductor structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-12075707-B2
Application number	US-202318358897-A
Country	US
Kind code	B2
Filing date	Jul 25, 2023
Priority date	Oct 27, 2020
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalls of the pillar structures.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a magnetic tunneling junction (MTJ) pillar comprising a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, a second magnetic layer overlying the tunnel barrier layer, and a protection layer;
a plurality of conductive particles on the protection layer; and
a cap dielectric layer over the conductive particles,
wherein the protection layer disposed above the first magnetic layer and surrounds the tunnel barrier layer and the second magnetic layer.

2. The semiconductor structure of claim 1 , wherein the magnetic tunneling junction (MTJ) pillar further comprises a top electrode layer overlying the second magnetic layer and the protection layer surrounds the top electrode layer.

3. The semiconductor structure of claim 1 , wherein the protection layer has polymer-rich chemistry.

4. The semiconductor structure of claim 1 , wherein the protection layer contains C, H, and O.

5. The semiconductor structure of claim 1 , wherein the cap dielectric layer comprises silicon nitride or silicon oxynitride.

6. The semiconductor structure of claim 4 , wherein the protection layer further comprises fluorine (F).

7. A semiconductor structure, comprising:
a bottom electrode layer;
a magnetic tunneling junction (MTJ) pillar over the bottom electrode, comprising a bottom magnetic layer, a tunnel barrier layer overlying the bottom magnetic layer, and a top magnetic layer overlying the tunnel barrier layer,
a top electrode layer over the MTJ pillar;
a protection layer over sidewalls of the top electrode layer, the top magnetic layer and the tunnel barrier layer, wherein the protection layer comprises carbon (C), hydrogen (H), and oxygen (O);
a plurality of conductive particles on the protection layer; and
a cap dielectric layer over the conductive particles.

8. The semiconductor structure of claim 7 , wherein the protection layer has polymer-rich chemistry.

9. The semiconductor structure of claim 7 , wherein the protection layer contains C, H, and O.

10. The semiconductor structure of claim 9 , wherein the protection layer further comprises fluorine (F).

11. The semiconductor structure of claim 7 , wherein the cap dielectric layer comprises silicon nitride or silicon oxynitride.

12. A memory device, comprising:
a plurality of magnetic tunneling junction (MTJ) pillars, each of which is formed on a bottom electrode and comprising a bottom magnetic layer, a tunnel barrier layer overlying the bottom magnetic layer, and a top magnetic layer overlying the tunnel barrier layer,
a plurality of top electrode layers, each of which is formed over the MTJ pillars, respectively;
a protection layer over sidewalls of each of the top electrode layers, the top magnetic layer and the tunnel barrier layer;
a plurality of conductive particles on the protection layer;
a cap dielectric layer over the conductive particles, and
a second dielectric layer between the MTJ pillars.

13. The memory device of claim 12 , wherein the second dielectric layer comprises TEOS oxide, PSG, BSG, BPSG, USG, FSG, SiOCH, flowable oxide, a porous oxide or combinations thereof.

14. The memory device of claim 12 , wherein the protection layer comprises polymer-rich chemistry.

15. The memory device of claim 12 , wherein the protection layer comprises C, H, and O.

16. The memory device of claim 15 , wherein the protection layer further comprises fluorine (F).

17. The memory device of claim 12 , wherein the cap dielectric layer comprises silicon nitride or silicon oxynitride.

18. The memory device of claim 12 , further comprising a plurality of conductive features penetrating through the cap dielectric layer and contacting the top electrodes, respectively.

19. The memory device of claim 18 , wherein the conductive features comprise copper, aluminum, tungsten, cobalt, or alloys thereof.

20. The memory device of claim 12 , wherein the second dielectric layer comprises a low-k dielectric material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jiann-Horng
• Li kun-yi
• Lin Han-Ting
• Lin Huan-Just
• Wang Chen-Jung
• Yang Sin-Yi

Classifications

• H10N50/80

  Constructional details · CPC title

• H10N50/01

  Manufacture or treatment · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title