Display substrate with virtual subpixels, manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-12075686-B2
Application number	US-202017280122-A
Country	US
Kind code	B2
Filing date	Jun 24, 2020
Priority date	Jun 24, 2020
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base substrate and a plurality of subpixels arranged on the base substrate in an array form. The plurality of subpixels includes a plurality of display subpixels at a display region of the display substrate and a plurality of virtual subpixels, and at least a part of the virtual subpixels are arranged adjacent to the display subpixels. The virtual subpixel includes a first potential signal line pattern, a virtual subpixel driving circuit including a virtual driving transistor and a first conductive connection member coupled to a gate electrode of the virtual driving transistor, and a second conductive connection member coupled to the first conductive connection member and the first potential signal line pattern.

First claim

What is claimed is:

1. A display substrate, comprising a base substrate and a plurality of subpixels arranged on the base substrate in an array form, wherein the plurality of subpixels comprises a plurality of display subpixels at a display region of the display substrate and a plurality of virtual subpixels, and at least a part of the virtual subpixels are arranged adjacent to the display subpixels;
the display subpixel comprises a display subpixel driving circuit, the display subpixel driving circuit comprises a driving transistor, a first transistor and a second transistor, and a gate electrode of the driving transistor is coupled to a second electrode of the first transistor and a second electrode of the second transistor; and
the virtual subpixel comprises a first potential signal line pattern, a virtual subpixel driving circuit comprising a virtual driving transistor and a first conductive connection member coupled to a gate electrode of the virtual driving transistor, and a second conductive connection member coupled to the first conductive connection member and the first potential signal line pattern.

2. The display substrate according to claim 1 , wherein
the first conductive connection member extends in a first direction,
the first potential signal line pattern comprises a first power source signal line pattern comprising a first portion extending in the first direction,
the second conductive connection member extends in a second direction intersecting the first direction, and the second conductive connection member is coupled to the first conductive connection member and the first portion of the first power source signal line pattern.

3. The display substrate according to claim 1 , wherein
the first potential signal line pattern comprises a first power source signal line pattern comprising a first portion and a second portion coupled to each other, the first portion extends in a first direction, the second portion extends in a second direction intersecting the first direction,
the first conductive connection member extends in the first direction, and
the second conductive connection member extends in the first direction and is coupled to the first conductive connection member and the second portion of the first power source signal line pattern.

4. The display substrate according to claim 3 , wherein the second portions in at least two virtual subpixels are coupled to each other in the second direction.

5. The display substrate according to claim 3 , wherein
the first portion and the second portion in at least one target virtual subpixel are formed integrally, and
the target virtual subpixel is an outermost virtual subpixel arranged at the display region in the first direction.

6. The display substrate according to claim 1 , wherein
the first potential signal line pattern comprises a first power source signal line pattern, and
the first conductive connection member, the second conductive connection member and the first power source signal line pattern are formed integrally.

7. The display substrate according to claim 1 , wherein the virtual subpixel further comprises;
a first gate line pattern and a first light-emission control signal line pattern each extending in the second direction, the first gate line pattern and the first light-emission control signal line pattern are arranged in the first direction, an orthogonal projection of the gate electrode of the virtual driving transistor onto the base substrate is located between an orthogonal projection of the first gate line pattern onto the base substrate and an orthogonal projection of the first light-emission control signal line pattern onto the base substrate, and
the orthogonal projection of the first gate line pattern onto the base substrate is located between an orthogonal projection of the second conductive connection member onto the base substrate and the orthogonal projection of the first light-emission control signal line pattern onto the base substrate.

8. The display substrate according to claim 7 , wherein the display subpixel comprises:
a second gate line pattern and a second light-emission control signal line pattern each extending in the second direction,
wherein the first gate line pattern in at least one virtual subpixel in the second direction is formed integrally with the second gate line pattern in a display subpixel arranged adjacent to the at least one virtual subpixel and arranged in a same row as the virtual subpixel in the second direction, and
the first light-emission control signal line pattern in at least one virtual subpixel in the second direction is formed integrally with the second light-emission control signal line pattern in a display subpixel arranged adjacent to the at least one virtual subpixel and arranged in a same row as the virtual subpixel in the second direction.

9. The display substrate according to claim 1 , wherein the first potential signal line pattern comprises a first power source signal line pattern, the virtual subpixel driving circuit further comprises:
a first storage capacitor, wherein the gate electrode of the virtual driving transistor is reused as a first electrode plate of the first storage capacitor, a second electrode plate of the first storage capacitor is located at a side of the first electrode plate away from the base substrate, an orthogonal projection of the second electrode plate onto the base substrate overlaps an orthogonal projection of a first portion of the first power source signal line pattern extending in the first direction onto the base substrate at an overlapping region where the second electrode plate is coupled to the first portion,
the display subpixel further comprises:
a second power source signal line pattern comprising a third portion extending in the first direction,
wherein the display subpixel driving circuit further comprises a second storage capacitor, the gate electrode of the driving transistor is reused as a third electrode plate of the second storage capacitor, a fourth electrode plate of the second storage capacitor is located at a side of the third electrode plate away from the base substrate, and an orthogonal projection of the fourth electrode plate onto the base substrate overlaps an orthogonal projection of the third portion of the second power source signal line pattern onto the base substrate at an overlapping region where the fourth electrode plate is coupled to the third portion, and
the second electrode plate in each of the virtual subpixels arranged in a same row in the second direction is formed integrally with the fourth electrode plate in the corresponding display subpixel in the row.

10. The display substrate according to claim 1 , wherein the display subpixel comprises:
a second power source signal line pattern comprising a third portion extending in the first direction, and
the first portion of the first power source signal line pattern in each of the virtual subpixels in a same column in the first direction is formed integrally with the third portion of the second power source signal line pattern in the corresponding display subpixel in the column.

11. The display substrate according to claim 1 , wherein
the virtual subpixel further comprises a first data line pattern extending in the first direction,
the display subpixel comprises a second data line pattern extending in the first direction, and
the first data line pattern in each of the virtual subpixels in a same column in the first direction is formed integrally with the second data line pattern in the corresponding display subpixel in the column.

12. The display substrate according to claim 1 , wherein the virtual sub

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Zhang Bo
• Dong Xiangdan
• Wang Junxi
• Yang Yixiang
• Wei Yulong
• Gou Jie
• Wang Rong

Classifications

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title