Display device

US10115337B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10115337-B2
Application numberUS-201514963528-A
CountryUS
Kind codeB2
Filing dateDec 9, 2015
Priority dateApr 29, 2015
Publication dateOct 30, 2018
Grant dateOct 30, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device includes a plurality of signal lines formed in a display area, a pixel array connected to the plurality of signal lines and including a plurality of pixels arranged in a matrix, a scan driving circuit and a data driving circuit formed in a non-display area and electrically connected to the plurality of signal lines, and a dummy pattern formed in the non-display area in a position adjacent to the pixel array along an outer boundary of the pixel array. The dummy pattern is formed to be parallel to a first pixel in a position spaced apart from the first pixel located at an edge of the pixel array in the non-display area by a predetermined distance.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising: a plurality of signal lines formed in a display area; a pixel array connected to the plurality of signal lines, the pixel array including a plurality of pixels each including a pixel pattern; a scan driving circuit and a data driving circuit located in a non-display area and electrically connected to the plurality of signal lines; and a dummy wiring line of a continuous thickness formed in the non-display area in a position adjacent to the pixel array, the dummy wiring line extending continuously along an entire periphery of the pixel array and having a shape of a closed loop around the pixel array, and wherein the dummy wiring line is spaced apart from the periphery of the pixel array by a predetermined distance, wherein the dummy wiring line comprises: a first dummy wiring line extending along a first side of the pixel array in a first direction; a second dummy wiring line extending along a second side of the pixel array parallel to the first side; a third dummy wiring line extending along a third side of the pixel array in a second direction perpendicular to the first direction; and a fourth dummy wiring line extending along a fourth side of the pixel array parallel to the third side, wherein at least one of the first and second dummy wiring lines is at an outer boundary region between the pixel array and the scan driving circuit, wherein at least one of the third and fourth dummy wiring lines is at an outer boundary between the pixel array and the data driving circuit, and wherein the first dummy wiring line is in a different layer from the third dummy wiring line at one end of the third dummy wiring line via a contact hole and a bridge. 2. The display device of claim 1 , wherein: the predetermined distance is the same as a distance between two adjacent pixel patterns. 3. The display device of claim 1 , wherein: a thickness of the dummy wiring line is the same as a thickness of the pixel patterns. 4. The display device of claim 1 , wherein: the first and second dummy wiring lines are disposed at a same layer as each other and at a different layer from the third and fourth dummy wiring lines and electrically connected to the third and fourth dummy wiring lines via a bridge, respectively. 5. The display device of claim 4 , wherein: the first and second dummy wiring lines are formed in an active layer, and the third and fourth dummy wiring lines are formed in a gate layer which is a different layer from the active layer. 6. The display device of claim 5 , wherein: the second dummy wiring lines is electrically connected to the fourth dummy wiring line via a contact hole and a bridge. 7. The display device of claim 1 , wherein: the first and second dummy wiring lines are formed in any one of an active layer, and a data metal layer that are different layers from each other and are included in an organic light emitting device. 8. The display device of claim 1 , wherein: both ends of a wiring line included in the dummy wiring line are connected to a ground wiring line or a power wiring line to be used as a static electricity shielding circuit. 9. The display device of claim 1 , wherein: a static electricity diode circuit is connected to the dummy wiring line.

Assignees

Inventors

Classifications

  • Layout of electrodes and connections · CPC title

  • Details of dummy pixels or dummy lines in flat panels · CPC title

  • Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

  • G09G3/3225Primary

    using an active matrix · CPC title

  • Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title

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Frequently asked questions

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What does patent US10115337B2 cover?
A display device includes a plurality of signal lines formed in a display area, a pixel array connected to the plurality of signal lines and including a plurality of pixels arranged in a matrix, a scan driving circuit and a data driving circuit formed in a non-display area and electrically connected to the plurality of signal lines, and a dummy pattern formed in the non-display area in a positi…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3225. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 30 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).