Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-12075611-B2
Application number	US-202117481583-A
Country	US
Kind code	B2
Filing date	Sep 22, 2021
Priority date	Feb 1, 2021
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a bit line extending in a first direction and comprising a metallic material;
a plurality of first active patterns and a plurality of second active patterns alternately disposed in the first direction and overlapping the bit line, wherein each of the plurality of first and second active patterns includes a horizontal portion and a vertical portion vertically extended from one end of the horizontal portion, one of the plurality of first active patterns and one of the plurality of second active patterns, which are adjacent to each other, being disposed to be symmetric with respect to each other;
a plurality of first word lines extending in a second direction different from the first direction and overlapping the bit line, each of the plurality of first word lines being disposed on a horizontal portion of a corresponding one of the plurality of first active patterns;
a plurality of second word lines extending in the second direction and overlapping the bit line, each of the plurality of second word lines being disposed on a horizontal portion of a corresponding one of the plurality of second active patterns; and
a plurality of intermediate structures, each intermediate structure being provided in at least one of a first gap region between a corresponding first word line of the plurality of first word lines and a corresponding second word line, adjacent to the corresponding first word line, of the plurality of second word lines, and a second gap region between a vertical portion of a corresponding first active pattern of the plurality of first active patterns and a vertical portion of a corresponding second active pattern, adjacent to the corresponding first active pattern, of the plurality of second active patterns.,
wherein each of the plurality of intermediate structures comprises an air gap in at least one of the first and second gap regions and a capping pattern covering a top of the air gap.

2. The semiconductor memory device of claim 1 ,
wherein the vertical portion of the corresponding first active pattern and the vertical portion of the corresponding second active pattern is disposed between the corresponding first word line and the corresponding second word line.

3. The semiconductor memory device of claim 1 ,
wherein each of the plurality of first and second word lines has a first side surface and a second side surface, which are opposite to each other,
wherein first side surfaces of each pair of first and second word lines among the plurality of first and second word lines are adjacent to vertical portions of a respective pair of first and second active patterns among the plurality of first and second active patterns, respectively,
wherein second side surfaces of each pair of first and second word lines face each other, and
wherein each pair of first and second word lines are disposed between the respective pair of first and second active patterns.

4. The semiconductor memory device of claim 1 ,
wherein top surfaces of the corresponding first and second word lines are located at a level lower than top surfaces of the vertical portions of the corresponding first and second active patterns.

5. The semiconductor memory device of claim 1 ,
wherein the bit line has a first width in the second direction,
wherein the horizontal portion of the corresponding first active pattern has a second width in the second direction, and
wherein the second width is larger than the first width.

6. The semiconductor memory device of claim 1 ,
wherein one of the plurality of first word lines and one of the plurality of second word lines, which are adjacent to each other, are spaced apart from each other by a first distance, and
wherein a vertical portion of one of the plurality of first active patterns and a vertical portion of one of the plurality of second active patterns, which are adjacent to each other, are spaced apart from each other by a second distance that is different from the first distance.

7. The semiconductor memory device of claim 6 ,
wherein the second distance is smaller than the first distance.

8. A semiconductor memory device, comprising:
a bit line extending in a first direction;
a plurality of active patterns disposed in the first direction and overlapping the bit line, wherein each of the plurality of active patterns includes a horizontal portion and a vertical portion, the horizontal portion extending along the bit line and the vertical portion vertically extending from one end of the horizontal portion;
a plurality of first word lines extending in a second direction different from the first direction and overlapping the bit line, each of the plurality of first word lines being disposed on an upper surface of a horizontal portion of a corresponding one of the plurality of active patterns, wherein the upper surface of the horizontal portion is higher than an upper surface of the bit line; and
a plurality of second word lines extending in the second direction and overlapping the bit line, each of the plurality of second word lines being disposed on an upper surface of a horizontal portion of a corresponding one of the plurality of active patterns;
a first insulating pattern filling a space between the pair of one of the plurality of first word lines and one of the plurality of second word lines, which are adjacent to each other;
a second insulating pattern filling a space between the vertical portions of the pair of active patterns, which are adjacent to each other; and
a shielding pattern disposed in a space defined by the second insulating pattern and between the vertical portions of the pair of active patterns, which are adjacent to each other,
wherein a pair of one of the plurality of first word lines and one of the plurality of second word lines, which are adjacent to each other, are spaced apart from each other by a first distance, and
wherein vertical portions of a first pair of active patterns of the plurality of active patterns, which are adjacent to each other, are spaced apart from each other by a second distance that is larger than the first distance.

9. The semiconductor memory device of claim 8 ,
wherein the shielding pattern comprises a metallic material or a two-dimensional conductive material.

10. The semiconductor memory device of claim 8 ,
wherein the shielding pattern extends in the second direction.

11. The semiconductor memory device of claim 8 , further comprising:
a first insulating pattern filling a space between the pair of one of the plurality of first word lines and one of the plurality of second word lines, which are adjacent to each other; and
a second insulating pattern filling a space between the vertical portions of the pair of active patterns, which are adjacent to each other,
wherein a dielectric constant of the second insulating pattern is lower than a dielectric constant of the first insulating pattern.

12. The semiconductor memory device of claim 8 ,
wherein top surfaces of the pair of one of the plurality of first word lines and one of the plurality of second word lines are located at a level lower than top surfaces of the vertical portions of the pair of active patterns.

13. The semiconductor memory device of claim 8 , further comprising:
a plurality of first data storage patterns connected to a plurality of first active patterns of the plurality of active patterns, respectively; and
a plurality of second data storage patterns connected to a plurality of second active patterns of the plurality of active patterns, respectively.

14. The semiconductor memory device of claim 13 ,

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Wonsok
• Ryu Min Tae
• Song Woo Bin
• Lee Kiseok
• Lee Minsu
• Cho Min Hee

Classifications

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D62/102

  Constructional design considerations for preventing surface leakage or controlling electric field concentration · CPC title

• H10D99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10B12/05

  Making the transistor · CPC title