Flexible compression header and code generation

Patent metadata

Field	Value
Publication number	US-12074618-B2
Application number	US-202017128787-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Dec 21, 2020
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

An embodiment of an integrated circuit may comprise a hardware compressor to compress data, the hardware compressor including circuitry to store input data in a history buffer, compute one or more code tables based on the input data, and compute a compression stream header based on the computed one or more code tables. Other embodiments are disclosed and claimed.

First claim

What is claimed is:

1. An integrated circuit, comprising:
an input/output (I/O) fabric interface; and
a hardware compressor coupled to the I/O fabric interface, the hardware compressor including circuitry to:
store input data in a history buffer;
compute one or more code tables based on the input data;
compute a compression stream header based on the computed one or more code tables; and
provide multiple modes of operation for the hardware compressor, wherein, in one mode of operation, the circuitry is further to:
store an entire set of job data in the history buffer in response to a single job for the hardware compressor where a size of the job data is less than or equal to a size of the history buffer;
compute the one or more code tables for the job data in response to the single job;
compute the compression stream header based on the computed one or more code tables for the job data in response to the single job; and
generate compressed output data for the job data stored in the history buffer based on the computed one or more code tables and the computed compression stream header in response to the single job.

2. The integrated circuit of claim 1 , wherein, in one mode of operation, the circuitry is further to:
store the computed one or more code tables and the computed compression stream header to memory in response to a first job for the hardware compressor with job data that exceeds a size of the history buffer; and
generate compressed output data for the job data based on the stored one or more code tables and the stored compression stream header in response to a second job for the hardware compressor.

3. The integrated circuit of claim 1 , wherein, in one mode of operation, the circuitry is further to:
read statistics from the input data; and
compute the one or more code tables and the compression stream header based on the read statistics.

4. The integrated circuit of claim 1 , wherein, in one mode of operation, the circuitry is further to:
output the computed one or more code tables without the compression stream header.

5. The integrated circuit of claim 1 , wherein, in one mode of operation, the circuitry is further to:
replace a count of zero for a possible token with a non-zero value.

6. The integrated circuit of claim 1 , wherein, in one mode of operation, the circuitry is further to:
calculate an expected compressed size for both canned codes and dynamic codes after a first pass; and
load a set of code tables and a compression stream header for a second pass that corresponds to either dynamic codes or canned codes based on a lower result of the respective calculated expected compressed sizes.

7. The integrated circuit of claim 1 , wherein the circuitry is further to:
set a maximum code length limit based on a user configurable parameter.

8. A method, comprising:
storing input data in a history buffer of a hardware compressor;
computing one or more code tables by the hardware compressor based on the input data;
computing a compression stream header by the hardware compressor based on the computed one or more code tables; and
providing multiple modes of operation for the hardware compressor, wherein, in one mode of operation, the method further comprises:
storing an entire set of job data in the history buffer in response to a single job for the hardware compressor where a size of the job data is less than or equal to a size of the history buffer;
computing the one or more code tables for the job data in response to the single job;
computing the compression stream header based on the computed one or more code tables for the job data in response to the single job; and
generating compressed output data for the job data stored in the history buffer based on the computed one or more code tables and the computed compression stream header in response to the single job.

9. The method of claim 8 , wherein, in one mode of operation, the method further comprises:
storing the computed one or more code tables and the computed compression stream header to memory in response to a first job for the hardware compressor with job data that exceeds a size of the history buffer; and
generating compressed output data for the job data based on the stored one or more code tables and the stored compression stream header in response to a second job for the hardware compressor.

10. The method of claim 8 , wherein, in one mode of operation, the method further comprises:
reading statistics from the input data; and
computing the one or more code tables and the compression stream header based on the read statistics.

11. The method of claim 8 , wherein, in one mode of operation, the method further comprises:
outputting the computed one or more code tables without the compression stream header.

12. The method of claim 8 , wherein, in one mode of operation, the method further comprises:
replacing a count of zero for a possible token with a non-zero value.

13. The method of claim 8 , wherein, in one mode of operation, the method further comprises:
calculating an expected compressed size for both canned codes and dynamic codes after a first pass; and
loading a set of code tables and a compression stream header for a second pass that corresponds to either dynamic codes or canned codes based on a lower result of the respective calculated expected compressed sizes.

14. The method of claim 8 , further comprising:
setting a maximum code length limit based on a user configurable parameter.

15. An apparatus, comprising:
two or more hardware accelerator engines;
memory communicatively coupled to the two or more hardware accelerator engines to store one or more jobs for the two or more hardware accelerator engines; and
a controller communicatively coupled to the memory and the two or more hardware accelerator engines to control the one or more jobs for the two or more hardware accelerator engines;

wherein each of the two or more hardware accelerator engines includes a hardware decompressor and access to a hardware compressor shared among the two or more hardware accelerator engines, the hardware compressor including circuitry to:
store input data in a history buffer; compute one or more code tables based on the input data; and compute a compression stream header based on the computed one or more code tables.

16. The apparatus of claim 15 , wherein the circuitry is further to:
provide multiple modes of operation for the hardware compressor.

17. The apparatus of claim 16 , wherein, in one mode of operation, the circuitry is further to:
store an entire set of job data in the history buffer in response to a single job for the hardware compressor where a size of the job data is less than or equal to a size of the history buffer;
compute the one or more code tables for the job data in response to the single job;
compute the compression stream header based on the computed one or more code tables for the job data in response to the single job; and
generate compressed output data for the job data stored in the history buffer based on the computed one or more code tables and the computed compression stream header in response to the single job.

18. The apparatus of claim 16 , wherein, in one mode of operation, the circuitry is further to:
store the computed one or more code tables and the computed compression stream header to the memory in response to a first job for the hardware compressor with job data that exceeds a size of the history buffer; and
generate compressed output data for the job dat

Assignees

• Intel Corp

Inventors

• Guilford James
• Gopal Vinodh
• Cutter Daniel

Classifications

• H03M7/3086

  employing a sliding window, e.g. LZ77 · CPC title

• G06F9/461

  Saving or restoring of program or task context · CPC title

• H03M7/42 Primary

  using table look-up for the coding or decoding process, e.g. using read-only memory {(H03M7/4006 takes precedence)} · CPC title

• H03M7/4043 Primary

  Adaptive prefix coding · CPC title

• H03M7/40 Primary

  Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code · CPC title