Track charge loss based on signal and noise characteristics of memory cells collected in calibration operations

Patent metadata

Field	Value
Publication number	US-12073899-B2
Application number	US-202117536462-A
Country	US
Kind code	B2
Filing date	Nov 29, 2021
Priority date	Aug 7, 2020
Publication date	Aug 27, 2024
Grant date	Aug 27, 2024

Abstract

A memory sub-system to track charge loss in memory cells and shifts of voltages optimized to read the memory cells. For example, a memory device can measure signal and noise characteristics of a group of memory cells to calculate an optimized read voltage of the group of memory cells. The memory sub-system having the memory device can determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage. The memory sub-system tracks changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss.

First claim

What is claimed is:

1. A device, comprising:
memory cells; and
a logic circuit configured to:
receive data representative of signal and noise characteristics of the memory cells;
determine, based on the signal and noise characteristics, a read voltage to read the memory cells; and
calculate, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells; and

a read circuit configured to apply voltages to the memory cells to determine states of the memory cells under the voltages applied to the memory cells; and
an integrated circuit package configured to enclose the memory cells, the logic circuit, and the read circuit.

2. The device of claim 1 , wherein the logic circuit is further configured to:
measure, using the read circuit, the signal and noise characteristics of the memory cells; and
determine, based on the signal and noise characteristics, a bit error rate in data retrievable from the memory cells using the read voltage, wherein the amount of charge loss is determined based at least in part on the bit error rate.

3. The device of claim 2 , wherein the logic circuit is further configured to track the read voltage in relation with the amount of charge loss.

4. The device of claim 2 , wherein the logic circuit is further configured to track, based at least in part on the read voltage and the amount of charge loss, changes in read voltage in relation with charge loss.

5. The device of claim 2 , wherein the signal and noise characteristics are configured to count differences over a plurality of test voltages, each count difference over two adjacent test voltages being a difference between:
a first count of a subset of the memory cells having a predetermined state when a first one of the adjacent test voltages is applied on the memory cells, and
a second count of a subset of the memory cells having the predetermined state when a second one of the adjacent test voltages is applied on the memory cells.

6. The device of claim 5 , wherein the logic circuit is configured to determine the read voltage based on a local minimum of a distribution of count difference over the plurality of test voltages.

7. The device of claim 6 , wherein the logic circuit is configured to calculate the amount of charge loss based on the read voltage.

8. The device of claim 7 , wherein the logic circuit is further configured to:
generate, using the read circuit, first data retrieved from the memory cells using the read voltage;
decode, using an error detection and recovery technique, the first data, to identify second data stored in the memory cells; and
count bit errors in the first data identified using the error detection and recovery technique.

9. The device of claim 7 , wherein the memory cells are configured to store multiple bits per memory cell and have a plurality of voltage levels for reading; and the read voltage is at a highest level among the plurality of voltage levels.

10. A method, comprising:
receiving, in a memory device, data representative of signal and noise characteristics of memory cells in the memory device;
determining, by the memory device based on the signal and noise characteristics, a read voltage;
determining data stored in the memory device from states of the memory cells subjected to the read voltage;
calculating, based at least in part on the characteristics, an amount of charge loss in the memory cells; and
applying a plurality of test voltages to the memory cells to determine states of the memory cells subjected to the test voltages respectively.

11. The method of claim 10 , further comprising:
determining a plurality of counts for the plurality of test voltages respectively, wherein each count in the plurality of counts for a respective test voltage is a number of a subset of the memory cells having a predetermined state when the memory cells are subjected to the respective test voltage; and
computing count differences between the counts for adjacent ones of the plurality of test voltages, wherein the signal and noise characteristics are configured to identify the count differences.

12. The method of claim 11 , further comprising:
generating first data represented by states of the memory cells when subjected to at least the read voltage;
decoding, using an error detection and recovery technique, the first data, to identify second data stored in the memory cells; and
determine, based on the decoding, a bit error rate in the first data to calculate the amount of charge loss.

13. The method of claim 12 , further comprising:
tracking the read voltage in relation with the amount of charge loss.

14. The method of claim 12 , further comprising:
tracking, based at least in part on the read voltage and the amount of charge loss, changes in read voltages of the memory cells.

15. The method of claim 12 , wherein the read voltage is determines based on an estimate of local minimum of the count differences over the plurality of test voltages.

16. The method of claim 15 , wherein the memory cells are configured to store multiple bits per memory cell and have a plurality of voltage levels for reading; and the read voltage is at a highest level among the plurality of voltage levels.

17. An apparatus, comprising:
a processing device; and
a memory device enclosed within an integrated circuit package and connected to the processing device, the memory device having:
memory cells;
a first circuit operable to apply voltages to the memory cells to determine states of the memory cells subjected to the voltages;
a second circuit configured to:
generate, using the first circuit, data representative of signal and noise characteristics of the memory cells;
determine, based on the signal and noise characteristics, a read voltage of the memory cells; and
generate, using the first circuit, first data representative states of the memory cells subject to voltages including the read voltage wherein the apparatus is further configured to:
determine second data stored in the memory cells based on the first data; and
calculate, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells.

18. The apparatus of claim 17 , wherein the first circuit is further configured to:
apply a plurality of test voltages to the memory cells to determine states of the memory cells subjected to the test voltages respectively;
determine a plurality of counts for the plurality of test voltages respectively, wherein each count in the plurality of counts for a respective test voltage is a number of a subset of the memory cells having a predetermined state when the memory cells are subjected to the respective test voltage; and
compute count differences between the counts for adjacent ones of the plurality of test voltages;
wherein the signal and noise characteristics are configured to identify the count differences; and
wherein the memory device is configured to determine the read voltage based on an estimate of local minimum of the count differences over the plurality of test voltages.

19. The apparatus of claim 18 , is further configured to track, based at least in part on the read voltage and the amount of charge loss, changes in read voltages of the memory cells.

20. The apparatus of claim 17 , wherein the apparatus is further configured to:
determine second data stored in the memory cells based on the first data; and
calculate, based at least in part on the signal and noise characteristics, an amoun

Assignees

• Micron Technology Inc

Inventors

• Parthasarathy Sivagnanam
• Fitzpatrick James
• Khayat Patrick Robert
• Alhussien Abdelhakim S

Classifications

• G06F18/214

  Generating training patterns; Bootstrap methods, e.g. bagging or boosting · CPC title

• G11C29/14

  Implementation of control logic, e.g. test mode decoders · CPC title

• G11C7/02 Primary

  with means for avoiding parasitic signals · CPC title

• G06N20/00

  Machine learning · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title