Systems and techniques for jitter reduction

Patent metadata

Field	Value
Publication number	US-12068751-B2
Application number	US-202217852657-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Jun 29, 2022
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A device includes a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal. The device also includes an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal.

First claim

What is claimed is:

1. A device, comprising:
a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal; and
an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal, wherein the clock adjustment circuitry comprises:
an edge detector circuit that generates an output clock signal having a third frequency as a multiple of the second frequency with a first duty cycle that differs from a second duty cycle of the internal clock signal; and
a duty cycle corrector comprising a duty cycle adjustment circuit that when in operation adjusts the first duty cycle of output clock signal.

2. The device of claim 1 , wherein edge detector circuit comprises a first input that when in operation receives the internal clock signal and a first output that when in operation transmits the output clock signal having the third frequency as a multiple of the second frequency.

3. The device of claim 2 , wherein the edge detector circuit comprises:
at least one delay circuit coupled to the first input; and
an XOR circuit, comprising:
a second input coupled to the first input; and
a third input coupled to a second output of the at least one delay circuit.

4. The device of claim 3 , wherein the XOR circuit when in operation generates the output clock signal having the third frequency as equivalent to the first frequency.

5. The device of claim 2 , wherein the duty cycle corrector is coupled to the edge detector circuit, wherein the duty cycle corrector comprises a second input that when in operation receives the output clock signal.

6. The device of claim 1 , wherein the duty cycle corrector comprises a duty cycle detection circuit coupled to the duty cycle adjustment circuit, wherein when in operation the duty cycle adjustment circuit adjusts the duty cycle of the output clock signal based upon an adjustment signal transmitted from the duty cycle detection circuit to the duty cycle adjustment circuit.

7. The device of claim 1 , wherein the duty cycle corrector when in operation adjusts the duty cycle of the output clock signal to a predetermined duty cycle.

8. The device of claim 7 , wherein the duty cycle corrector comprises a second output, wherein the duty cycle corrector when in operation transmits the phase controlled internal clock signal as having the predetermined duty cycle.

9. A device, comprising:
a first clock doubler circuit that when in operation receives an input clock signal having a first frequency, wherein the first clock doubler circuit comprises:
a first edge detector circuit comprising a first input that when in operation receives the input clock signal and a first output that when in operation transmits an output clock signal having a second frequency as a multiple of the first frequency with a first duty cycle that differs from a second duty cycle of the input clock signal; and
a first duty cycle corrector coupled to the first edge detector circuit, wherein the first duty cycle corrector comprises a second input that when in operation receives the output clock signal and a second output that when in operation transmits a first duty cycle adjusted output clock signal having the second duty cycle of the input clock signal.

10. The device of claim 9 , comprising:
a second clock doubler circuit coupled to the first clock doubler circuit, wherein the second clock doubler circuit when in operation receives the first duty cycle adjusted output clock signal having the second frequency and the second duty cycle of the input clock signal, wherein the second clock doubler circuit comprises:
a second edge detector circuit comprising a third input that when in operation receives the first duty cycle adjusted output clock signal and a third output that when in operation transmits a second output clock signal having a third frequency as a multiple of the first frequency and the second frequency with a third duty cycle that differs from the second duty cycle of the input clock signal; and
a second duty cycle corrector coupled to the second edge detector circuit, wherein the second duty cycle corrector comprises a fourth input that when in operation receives the second output clock signal and a fourth output that when in operation transmits a second duty cycle adjusted output clock signal having the second duty cycle of the input clock signal.

11. The device of claim 10 , wherein the first edge detector circuit comprises:
at least one delay circuit coupled to the first input; and
an XOR circuit, comprising:
a fifth input coupled to the first input; and
a sixth input coupled to a fifth output of the at least one delay circuit.

12. The device of claim 11 , wherein the first duty cycle corrector comprises:
a duty cycle adjustment circuit that when in operation adjusts the first duty cycle of the output clock signal; and
a duty cycle detection circuit coupled to the duty cycle adjustment circuit, wherein when in operation the duty cycle adjustment circuit adjusts the first duty cycle of the output clock signal based upon an adjustment signal transmitted from the duty cycle detection circuit to the duty cycle adjustment circuit to the second duty cycle of the input clock signal.

13. The device of claim 12 , comprising:
a third clock doubler circuit coupled to the second clock doubler circuit, wherein the third clock doubler circuit when in operation receives the second duty cycle adjusted output clock signal having the third frequency and generates a third duty cycle adjusted output clock signal having a fourth frequency; and
a fourth clock doubler circuit coupled to the third clock doubler circuit, wherein the fourth clock doubler circuit when in operation receives the third duty cycle adjusted output clock signal having the fourth frequency and generates a fourth duty cycle adjusted output clock signal having a fifth frequency.

14. The device of claim 13 , comprising an input output interface coupled to the fourth clock doubler circuit, wherein the fourth clock doubler circuit comprises a sixth output that when in operation transmits the fourth duty cycle adjusted output clock signal to the input output interface.

15. The device of claim 14 , wherein the input output interface utilizes the fourth duty cycle adjusted output clock signal in a data read operation of the device.

16. The device of claim 15 , wherein the first clock doubler circuit comprises a seventh output, wherein the seventh output when in operation transmits the first duty cycle adjusted output clock signal to a command decoder of the device.

17. A system, comprising:
a clock divider circuit that when in operation receives a clock signal having a first frequency, generates an internal clock signal having a second frequency based on the clock signal, and transmits the internal clock signal to a command decoder of the system; and
an internal clock generator coupled to the clock divider circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal comprising clock edges based upon a single c

Assignees

• Micron Technology Inc

Inventors

• Stave Eric J
• Gomm Tyler J

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03K5/1534

  Transition or edge detectors · CPC title

• H03K5/00006

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title