Multi-phase switching regulators with hybrid inductors and per phase frequency control

Patent metadata

Field	Value
Publication number	US-12068684-B2
Application number	US-202017030132-A
Country	US
Kind code	B2
Filing date	Sep 23, 2020
Priority date	Sep 23, 2020
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.

First claim

What is claimed is:

1. An inductor array, comprising:
a first inductor with a first inductance, and wherein the first inductor is switched at a first frequency;
a second inductor with a second inductance that is different than the first inductance, and wherein the second inductor is switched at a second frequency that is different than the first frequency; and
a third inductor with a third inductance, wherein the third inductance is different than the first inductance and the second inductance, and wherein the third inductor is switched at a third frequency that is different than the first frequency and the second frequency.

2. The inductor array of claim 1 , wherein the first inductor and the second inductor are within the same voltage domain.

3. The inductor array of claim 1 , wherein the first inductance is larger than the second inductance, and wherein the first frequency is lower than the second frequency.

4. The inductor array of claim 3 , wherein the second frequency is an integer multiple of the first frequency.

5. The inductor array of claim 3 , further comprising:
a frequency divider coupled to the first inductor.

6. The inductor array of claim 5 , wherein the frequency divider is a D flip-flop based frequency divider.

7. The inductor array of claim 3 , further comprising:
a frequency multiplier coupled to the second inductor.

8. The inductor array of claim 7 , wherein the frequency multiplier comprises a XOR logic gate with a first input being an input frequency and a second input being the input frequency delayed by ninety degrees.

9. The inductor array of claim 1 , wherein the first inductor is an air core inductor and the second inductor is an air core inductor, and wherein the first inductance is larger than the second inductance.

10. The inductor array of claim 1 , wherein the first inductor is a magnetic inductor, and the second inductor is an air core inductor, and wherein the first inductance is larger than the second inductance.

11. The inductor array of claim 10 , wherein the magnetic inductor is coaxial magnetic integrated inductor, a planar magnetic integrated inductor, or a discrete magnetic inductor.

12. The inductor array of claim 1 , wherein the first inductor and the second inductor are magnetic inductors, and wherein the first inductance is larger than the second inductance.

13. The inductor array of claim 1 , further comprising:
a fourth inductor with the third inductance, and wherein the fourth inductor is switched at the third frequency.

14. An integrated voltage regulator, comprising:
a plurality of voltage domains, wherein individual ones of the plurality of voltage domains comprises:
a plurality of inductors, wherein three or more of the plurality of inductors are operated at different phases from one another, and
wherein the three or more of the plurality of inductors are switched at different frequencies from one another.

15. The integrated voltage regulator of claim 14 , wherein a first inductor of the plurality of inductors has a first inductance, and wherein the first inductor is switched at a first frequency, and wherein a second inductor of the plurality of inductors has a second inductance that is larger than the first inductance, and wherein the second inductor is switched at a second frequency that is lower than the first frequency.

16. The integrated voltage regulator of claim 15 , wherein the first inductor is an air core inductor and the second inductor is an air core inductor.

17. The integrated voltage regulator of claim 15 , wherein the first inductor is an air core inductor and the second inductor is a magnetic inductor, and wherein the magnetic inductor comprises a coaxial magnetic integrated inductor, a planar magnetic integrated inductor, or a discrete inductor.

18. The integrated voltage regulator of claim 15 , wherein the first inductor is a magnetic inductor and the second inductor is a magnetic inductor.

19. The integrated voltage regulator of claim 15 , further comprising:
a frequency multiplier connected to the first inductor.

20. The integrated voltage regulator of claim 15 , further comprising:
a frequency divider connected to the second inductor.

21. The integrated voltage regulator of claim 14 , wherein the integrated voltage regulator is a fully integrated voltage regulator (FIVR).

22. An electronic system, comprising:
a package substrate;
a first inductor embedded in the package substrate, wherein the first inductor has a first inductance;
a second inductor embedded in the package substrate, wherein the second inductor has a second inductance that is different than the first inductance;
a third inductor embedded in the package substrate, wherein the third inductor has a third inductance that is different than the first inductance and the second inductance;
a die electrically coupled to the package substrate, wherein the die comprises:
a voltage regulator circuitry block, wherein the voltage regulator circuitry block is electrically coupled to the first inductor, the second inductor and the third inductor, and wherein the voltage regulator circuitry block provides a first switching frequency to the first inductor, a second switching frequency that is different than the first switching frequency to the second inductor, and a third switching frequency that is different than the first switching frequency and the second switching frequency to the third inductor.

23. The electronic system of claim 22 , wherein the first inductor comprises:
a plated through hole via; and
a magnetic shell surrounding the plated through hole via, and wherein the second inductor comprises one or more conductive loops.

24. The electronic system of claim 23 , wherein the first inductance is larger than the second inductance, and wherein the first switching frequency is lower than the second switching frequency.

25. The electronic system of claim 22 , further comprising:
a board, wherein the package substrate is electrically coupled to the board.

Assignees

• Intel Corp

Inventors

• Bharath Krishna
• Schaef Christopher
• Lambert William J
• Radhakrishnan Kaladhar

Classifications

• H10D1/20 Primary

  Inductors · CPC title

• H01F27/24

  Magnetic cores · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H01F17/06

  with core substantially closed in itself, e.g. toroid · CPC title

• H01F17/0006

  Printed inductances (printed coils for dynamo-electric machines H02K3/26; printed circuits H05K) · CPC title