Semiconductor device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-12068411-B2
Application number	US-201817040631-A
Country	US
Kind code	B2
Filing date	Mar 26, 2018
Priority date	Mar 26, 2018
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A semiconductor device includes: a substrate having a groove formed on a main surface; a drift region of a first conductivity type, the drift region having a portion disposed at a bottom part; a well region of a second conductivity type, the well region being disposed in one sidewall to be connected to the drift region; a first semiconductor region of the first conductivity type, the first semiconductor region being disposed on a surface of the well region in the sidewall to be away from the drift region; a second semiconductor region of the first conductivity type, the second semiconductor region being disposed to be opposed to the well region via the drift region; and a gate electrode opposed to the well region, the gate electrode being disposed in a gate trench that has an opening extending over the upper surfaces of the well region and the first semiconductor region.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate having a groove formed on a main surface of the substrate;
a drift region of a first conductivity type, the drift region being disposed from a first sidewall of the groove to a bottom part of the groove;
a well region of a second conductivity type, the well region being disposed along the first sidewall of the groove to be connected to the drift region and being connected to the drift region at the bottom part of the groove;
a first semiconductor region of the first conductivity type, the first semiconductor region being disposed on a surface of the well region along the first sidewall of the groove to be away from the drift region;
a second semiconductor region of the first conductivity type, the second semiconductor region being disposed at the bottom part of the groove to adjoin to the drift region to be adjacent to a second sidewall of the groove, and in proximity to the second sidewall to be opposed to and in parallel to the first sidewall of the groove; and
a gate electrode opposed to the well region, the gate electrode being disposed in a gate trench that has an opening extending over the upper surfaces of the well region and the first semiconductor region and extends in a depth direction of the groove,
wherein the drift region has a sidewall portion formed along the first sidewall of the groove from an opening of the groove and a bottom portion disposed at the bottom part of the groove, a lower end of the sidewall portion reaches below the bottom part of the groove, and the sidewall portion and the bottom portion are connected to each other.

2. The semiconductor device according to claim 1 , wherein
the well region is disposed on a surface of the drift region along the first sidewall of the groove.

3. The semiconductor device according to claim 1 , wherein
the substrate is an insulating substrate.

4. The semiconductor device according to claim 1 , wherein
at least a portion of the drift region has a structure in which a first conductivity type region and a second conductivity type region are disposed alternately along a longitudinal direction of the groove in which the first sidewall extends.

5. The semiconductor device according to claim 1 , wherein
at least the portion of the drift region disposed at the bottom part of the groove has a structure in which a first conductivity type region and a second conductivity type region are layered along the depth direction of the groove.

6. The semiconductor device according to claim 4 , wherein
impurity concentrations of the first conductivity type region and the second conductivity type region are set such that the first conductivity type region and the second conductivity type region are depleted by a depletion layer that spreads from a pn junction formed at the boundary between the first conductivity type region and the second conductivity type region, in an off state in which main electrical current flowing between the first semiconductor region and the second semiconductor region is cut off.

7. The semiconductor device according to claim 5 , wherein
impurity concentrations of the first conductivity type region and the second conductivity type region are set such that the first conductivity type region and the second conductivity type region are depleted by a depletion layer that spreads from a pn junction formed at the boundary between the first conductivity type region and the second conductivity type region, in an off state in which main electrical current flowing between the first semiconductor region and the second semiconductor region is cut off.

8. The semiconductor device according to claim 1 , further comprising:
a first main electrode disposed on a surface of the first semiconductor region along the first sidewall of the groove and electrically connected to the first semiconductor region;
a second main electrode disposed in the groove to be opposed to the first main electrode and electrically connected to the second semiconductor region; and
an isolation insulating film disposed between the first main electrode and the second main electrode and filling the inside of the groove, wherein
a portion of the isolation insulating film, the portion sandwiched between the first main electrode and the second main electrode, is divided by a dividing groove extending in parallel with the first sidewall of the groove.

9. The semiconductor device according to claim 1 , wherein the first semiconductor region extends in the depth direction of the groove from the opening of the groove.

10. A semiconductor device comprising:
a substrate having a groove formed on a main surface of the substrate;
a drift region of a first conductivity type, the drift region being disposed from a first sidewall of the groove to a bottom part of the groove;
a well region of a second conductivity type, the well region being disposed along the first sidewall of the groove to be connected to the drift region;
a first semiconductor region of the first conductivity type, the first semiconductor region being disposed on a surface of the well region along the first sidewall of the groove;
a second semiconductor region of the first conductivity type, the second semiconductor region being disposed at the bottom part of the groove to adjoin to the drift region to be adjacent to a second sidewall of the groove, and in proximity to the second sidewall to be opposed to the first sidewall of the groove; and
a gate electrode opposed to the well region, the gate electrode being disposed in a gate trench that has an opening extending over the upper surfaces of the well region and the first semiconductor region and extends in a depth direction of the groove,
wherein the well region is formed from the opening of the groove along the first sidewall of the groove, and wherein the drift region has a sidewall portion formed along the first sidewall of the groove from an opening of the groove and a bottom portion disposed at the bottom part of the groove, and a lower end of the well region reaches below the bottom part of the groove.

Assignees

• Nissan Motor
• Renault Sas

Inventors

• Marui Toshiharu
• Hayashi Tetsuya
• Numakura Keiichiro
• Ni Wei
• Tanaka Ryota
• Takemoto Keisuke

Classifications

• H10D64/01344

  in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D64/01346

  in a gaseous ambient using an oxygen or a water vapour, e.g. oxidation through a layer (H10D64/01344 takes precedence) · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/0289

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title