Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12068301-B2
Application number	US-202318297849-A
Country	US
Kind code	B2
Filing date	Apr 10, 2023
Priority date	Mar 19, 2018
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate;
a transistor provided on the substrate;
a first interconnection layer provided above the transistor;
a second interconnection layer provided above the first interconnection layer;
a plurality of bit lines provided above the second interconnection layer and respectively extending in a first direction;
a plurality of electrode layers stacked in a second direction perpendicular to the first direction above the plurality of bit lines;
a conductive layer provided above the plurality of electrode layers;
a plurality of columnar portions respectively extending in the second direction in the plurality of electrode layers and respectively including a semiconductor layer and a charge accumulating layer; and
a first via plug provided between and connecting a first bit line of the plurality of bit lines and a first interconnection in the second interconnection layer,
wherein
the first via plug has an elongated shape in the first direction in a plane perpendicular to the second direction and has a first width in the first direction, and
the first interconnection has a second width in the first direction greater than the first width.

2. The semiconductor device of claim 1 , further comprising a memory cell array including the plurality of electrode layers and a plurality of insulating layers that are alternately stacked in the second direction,
wherein the plurality of columnar portions are provided in the plurality of electrode layers and the plurality of insulating layers.

3. The semiconductor device of claim 1 , wherein the plurality of electrode layers function as word lines.

4. The semiconductor device of claim 1 , further comprising a second via plug provided above and in contact with the first bit line.

5. The semiconductor device of claim 4 , wherein a position where the second via plug contacts the first bit line is shifted from a position where the first via plug contacts the first bit line in the first direction.

6. The semiconductor device of claim 4 , wherein the second via plug has an elongated shape in the first direction in a plane perpendicular to the second direction and has a third width in the first direction smaller than the second width.

7. The semiconductor device of claim 1 , wherein
the first bit line includes a linear portion that extends in a straight-line shape or in a curved-line shape, and
the first via plug is provided under the linear portion.

8. The semiconductor device of claim 7 , wherein
the linear portion includes at least a straight-line portion that extends in a straight-line shape, and a bent portion that is bent with respect to the straight-line portion, and
the first via plug is provided under the straight-line portion.

9. The semiconductor device of claim 7 , wherein
the linear portion includes at least a straight-line portion that extends in a straight-line shape, and a bent portion that is bent with respect to the straight-line portion, and
the first via plug is provided under the bent portion.

Assignees

• Kioxia Corp

Inventors

• Iijima Jun
• Nakajima Yumi

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title