Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11652094-B2
Application number	US-202217692954-A
Country	US
Kind code	B2
Filing date	Mar 11, 2022
Priority date	Mar 19, 2018
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first chip including:
a substrate, and
a transistor provided on the substrate;

a second chip bonded to the first chip and including:
a first interconnection included in a plurality of interconnections in an interconnection layer,
a first via plug provided above and in contact with the first interconnection,
a first bit line provided above and in contact with the first via plug, and extending in a first direction parallel to a surface of the substrate,
a second via plug provided above and in contact with the first bit line, and
a columnar portion provided above and electrically connected to the second via plug, including a semiconductor layer and a charge accumulating layer, and extending in a second direction perpendicular to the surface of the substrate;

a metal pad body provided on a bonding surface of the first chip and the second chip, and electrically connecting the transistor of the first chip to the first interconnection of the second chip,
wherein
the first via plug has a first width in the first direction,
the first interconnection has a second width in the first direction, and
the second width of the first interconnection is greater than the first width of the first via plug.

2. The device of claim 1 , further comprising a memory cell array provided in the second chip, and including a plurality of electrode layers and a plurality of insulating layers that are alternately stacked,
wherein the columnar portion is provided in the plurality of electrode layers and the plurality of insulating layers.

3. The device of claim 1 , wherein the plurality of electrode layers function as word lines.

4. The device of claim 1 , wherein a position where the second plug contacts the first bit line is shifted from a position where the first plug contacts the first bit line in the first direction.

5. The device of claim 1 , wherein
the first bit line includes a linear portion that extends in a straight-line shape or in a curved-line shape, and
the first plug is provided under the linear portion.

6. The device of claim 5 , wherein
the linear portion includes at least a straight-line portion that extends in a straight-line shape, and a bent portion that is bent with respect to the straight-line portion, and
the first plug is provided under the straight-line portion.

7. The device of claim 5 , wherein
the linear portion includes at least a straight-line portion that extends in a straight-line shape, and a bent portion that is bent with respect to the straight-line portion, and
the first plug is provided under the bent portion.

Assignees

• Kioxia Corp

Inventors

• Iijima Jun
• Nakajima Yumi

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title