Display panel, splicing display panel and preparation method thereof

Patent metadata

Field	Value
Publication number	US-12068291-B2
Application number	US-201916978810-A
Country	US
Kind code	B2
Filing date	Nov 15, 2019
Priority date	Nov 15, 2019
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

The display panel includes a base substrate; and display areas arranged on the base substrate; each of the display areas includes pixel units; each of the pixel units includes sub-pixels; each of the sub-pixels includes a light-emitting chip; in any one of the display areas, a space between two adjacent columns of pixel units in a row direction has a first space size; and a space between two adjacent rows of pixel units in a column direction has a second space size; a space between two nearest display areas in the row direction has a third space size, and the third space size is approximately same as the first space size; and/or a space between two nearest display areas in the column direction has a fourth space size, and the fourth space size is approximately same as the second space size.

First claim

What is claimed is:

1. A display panel, comprising:
a base substrate; and
a plurality of display areas arranged on the base substrate in an array;
wherein,
each of the plurality of display areas comprises a plurality of pixel units;
each of the plurality of pixel units comprises a plurality of sub-pixels; and
each of the plurality of sub-pixels comprises a light-emitting chip;
wherein in any one of the plurality of display areas,
a space between two adjacent columns of pixel units in a row direction has a first space size; and
a space between two adjacent rows of pixel units in a column direction has a second space size;

wherein,
a space between two nearest columns of display areas among the plurality of display areas in the array in the row direction has a third space size, and the third space size is approximately same as the first space size;
and/or
a space between two nearest rows of display areas among the plurality of display areas in the array in the column direction has a fourth space size, and the fourth space size is approximately same as the second space size.

2. The display panel according to claim 1 , wherein,
sub-pixels in the each of the plurality of display areas are arranged in an array; and
the each of the plurality of the sub-pixels further comprises a driving circuit configured to drive the light-emitting chip.

3. The display panel according to claim 2 , wherein the each of the plurality of display areas further comprises:
a plurality of first signal driving lines and a plurality of second signal driving lines located between the base substrate and light-emitting chips of sub-pixels in the display area;
wherein the first signal driving lines and the second signal driving lines are crossed and insulated; and
driving circuits in each row of sub-pixels in the display area are electrically connected to a respective one of the first signal driving lines, and driving circuits in each column of sub-pixels in the display area are electrically connected to a respective one of the second signal driving lines.

4. The display panel according to claim 3 , wherein the each of the plurality of display areas further comprises:
a plurality of first signal transmission lines;
a plurality of second signal transmission lines; and
a driving chip electrically connected to the first signal transmission lines and the second signal transmission lines;
wherein the plurality of first signal transmission lines, the plurality of second signal transmission lines and the driving chip are located on a side, facing away from the light-emitting chips, of the base substrate; and
each of the first signal driving lines is electrically connected to a respective one of the first signal transmission lines through a corresponding first via hole penetrating through the base substrate; and each of the second signal driving lines is electrically connected to a respective one of the second signal transmission lines through a corresponding second via hole penetrating through the base substrate.

5. The display panel according to claim 4 , wherein each of the first signal driving lines corresponds to a respective one of first via holes; and the first via holes are located at a same end of the first signal driving lines.

6. The display panel according to claim 4 , wherein each of the first signal driving lines corresponds to a respective one of first via holes; a part of the first via holes are located at one end of the first signal driving lines, and a rest part of the first via holes are located at another end of the first signal driving lines.

7. The display panel according to claim 6 , wherein first via holes corresponding to odd-numbered rows of first signal driving lines are located at the one end of the first signal driving lines, and first via holes corresponding to even-numbered rows of first signal driving lines are located at the another end of the first signal driving lines.

8. The display panel according to claim 4 , wherein each of the first signal driving lines corresponds to respective two of first via holes; one of the two first via holes is located at one end of the first signal driving line, and another one of the two first via holes is located at another end of the first signal driving line.

9. The display panel according to claim 4 , wherein each of the second signal driving lines corresponds to a respective one of second via holes; and the second via holes are located at a same end of the second signal driving lines.

10. The display panel according to claim 4 , wherein each of the second signal driving lines corresponds to a respective one of the second via holes; a part of the second via holes are located at one end of the second signal driving lines, and a rest part of the second via holes are located at another end of the second signal driving lines.

11. The display panel according to claim 10 , wherein second via holes corresponding to odd-numbered columns of second signal driving lines are located at the one end of the second signal driving lines, and second via holes corresponding to even-numbered columns of second signal driving lines are located at the another end of the second signal driving lines.

12. The display panel according to claim 4 , wherein each of the second signal driving lines corresponds to respective two of second via holes; one of the two second via holes is located at one end of the second signal driving line, and another one of the two second via holes is located at another end of the second signal driving line.

13. A method for preparing the display panel according to claim 1 , comprising:
forming the plurality of display areas on the base substrate;
wherein,
each of the plurality of display areas comprises a plurality of pixel units;
each of the plurality of pixel units comprises a plurality of sub-pixels; and
each of the plurality of sub-pixels comprises a light-emitting chip;
wherein in any one of the plurality of display areas,
a space between two adjacent columns of pixel units in a row direction has a first space size; and
a space between two adjacent rows of pixel units in a column direction has a second space size;

wherein,
a space between two nearest display areas among the plurality of display areas in the row direction has a third space size, and the third space size is approximately same as the first space size;
and/or
a space between two nearest display areas among the plurality of display in the column direction has a fourth space size, and the fourth space size is approximately the same as the second space size.

14. The method according to claim 13 , wherein said forming the plurality of display areas comprises:
in each of the plurality of display areas on the base substrate:
forming a plurality of first signal driving lines and a plurality of second signal driving lines, wherein the first signal driving lines and the second signal driving lines are crossed and insulated;
forming a plurality of first signal transmission lines and a plurality of second signal transmission lines on a side, facing away from the first signal driving lines, of the base substrate;
forming a plurality of first via holes and a plurality of second via holes; and
forming a conductive material in each of the first via holes and each of the second via holes, so that each of the first signal driving lines is electrically connected to a respective one of the first signal transmission lines through a corresponding first via hole, and each of the second signal driving lines is electrically connected to a respective one of the second signal transmission lines through a correspondin

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Qu Lianjie
• Yang Hong
• Zhao Hebin
• Qiu Yun

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10H20/0364

  of interconnections · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/01

  Manufacture or treatment · CPC title