Display Panel and Method of Fabricating the Same, and Display Device

Patent metadata

Field	Value
Publication number	US-2016372489-A1
Application number	US-201514905380-A
Country	US
Kind code	A1
Filing date	Aug 18, 2015
Priority date	Jan 14, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

The present invention provides a display panel, a fabricating method thereof and a display device. The display panel comprises a pixel region and a fan-out region, first signal lines and second signal lines are provided to intersect each other in the pixel region, and extend into the fan-out region, respectively, a first insulation layer is provided between the first signal lines and the second signal lines, a second insulation layer is provided on the second signal lines, the second insulation layer comprises at least four layers of structures, and a density of each layer of structure of the second insulation layer decreases gradually along a direction away from the first insulation layer. A size of the via hole formed in the second insulation layer by etching is smaller than that of the via hole formed in the prior art.

First claim

1 . A display panel comprising a pixel region and a fan-out region, a plurality of first signal lines and a plurality of second signal lines being provided to intersect each other in the pixel region, the first signal lines and the second signal lines extending into the fan-out region, respectively, wherein
a first insulation layer is provided between the first signal lines and the second signal lines, a second insulation layer is provided on the second signal lines, the second insulation layer comprises at least four layers of structures, and a density of each layer of structure of the second insulation layer decreases gradually along a direction away from the first insulation layer.

2 . The display panel of claim 1 , wherein each layer of structure of the second insulation layer is made of the same material.

3 . The display panel of claim 1 , further comprising a driving circuit region, wherein the fan-out region is provided between the pixel region and the driving circuit region, the driving circuit region comprises first driving chips and second driving chips, the first driving chip is electrically connected with the first signal lines through first via holes penetrating through the first insulation layer and the second insulation layer in the fan-out region, and the second driving chip is electrically connected with the second signal lines through second via holes penetrating through the second insulation layer in the fan-out region.

4 . The display panel of claim 3 , wherein the second via hole has a step-like inner wall, and each step is positioned at an interface between any two adjacent layers of structures in the second insulation layer.

5 . The display panel of claim 4 , wherein a diameter of a circle formed by each step increases sequentially along the direction away from the first insulation layer.

6 . The display panel of any one of claim 1 , wherein the second insulation layer comprises four layers of structures.

7 . The display panel of claim 6 , wherein thicknesses of the four layers of structures of the second insulation layer are sequentially in ranges of 10 nm to 50 nm, 50 nm to 500 nm, 50 nm to 500 nm and 10 nm to 50 nm along the direction away from the first insulation layer.

8 . The display panel of claim 6 , wherein etch rates of the four layers of structures of the second insulation layer are sequentially in ranges of 300 nm/min to 600 nm/min, 300 nm/min to 800 nm/min, 300 nm/min to 1000 nm/min and 300 nm/min to 1500 nm/min along the direction away from the first insulation layer.

9 . The display panel of claim 8 , wherein the etch rate of the second layer of structure is smaller than that of the third layer of structure by 100 nm/min to 700 nm/min in the four layers of structures of the second insulation layer.

10 . The display panel of claim 1 , wherein the first signal line is a gate line, the second signal line is a data line, the first driving chip is a gate driving chip, and the second driving chip is a source driving chip.

11 . The display panel of claim 1 , wherein the first signal line is a data line, the second signal line is a gate line, the first driving chip is a source driving chip, and the second driving chip is a gate driving chip.

12 . A method of fabricating a display panel, the display panel comprising a pixel region and a fan-out region, the method comprising steps of sequentially forming first signal lines, a first insulation layer, second signal lines and a second insulation layer on a substrate, the first signal lines and the second signal lines being provided in the pixel region to intersect each other, and extending from the pixel region into the fan-out region, respectively, wherein the step of forming the second insulation layer comprises sequentially forming, on the substrate having the second signal lines formed thereon, at least four layers of insulation films whose densities decrease gradually, to form the layers of structures of the second insulation layer.

13 . The method of claim 12 , wherein each layer of structure of the second insulation layer is made of the same material.

14 . The method of claim 13 , wherein the second insulation layer comprises four layers of structures, the step of sequentially forming the four layers of structures of the second insulation layer on the substrate having the second signal lines formed thereon comprises: forming the second insulation layer by a chemical vapor deposition process using reaction gases of NH3, N2 and SiH4 under a temperature ranging from 250° C. to 400° C., wherein when forming the first layer of structure of the second insulation layer, a flow rate of SiH4 ranges from 500 sccm to 1500 sccm, a flow rate of NH3 ranges from 2000 sccm to 4000 sccm, a flow rate of N2 ranges from 10000 sccm to 30000 sccm, a reaction power ranges from 3000W to 6000W, a reaction pressure ranges from 500 mtorr to 1000 mtorr, and a reaction distance ranges from 500 mils to 1500 mils;
when forming the second layer of structure of the second insulation layer, the flow rate of SiH4 ranges from 1000 sccm to 2000 sccm, the flow rate of NH3 ranges from 3000 sccm to 5000 sccm, the flow rate of N2 ranges from 10000 sccm to 30000 sccm, the reaction power ranges from 3000W to 7000W, the reaction pressure ranges from 800 mtorr to 1500 mtorr, and the reaction distance ranges from 800 mils to 1500 mils;
when forming the third layer of structure of the second insulation layer, the flow rate of SiH4 ranges from 1000 sccm to 2000 sccm, the flow rate of NH3 ranges from 3000 sccm to 7000 sccm, the flow rate of N2 ranges from 10000 sccm to 30000 sccm, the reaction power ranges from 3000W to 7000W, the reaction pressure ranges from 1000 mtorr to 2500 mtorr, and the reaction distance ranges from 800 mils to 1500 mils; and
when forming the fourth layer of structure of the second insulation layer, the flow rate of SiH4 ranges from 1000 sccm to 2000 sccm, the flow rate of NH3 ranges from 4000 sccm to 8000 sccm, the flow rate of N2 ranges from 10000 sccm to 30000 sccm, the reaction power ranges from 5000W to 7000W, the reaction pressure ranges from 2000 mtorr to 3000 mtorr, and the reaction distance ranges from 800 mils to 1500 mils.

15 . The method of claim 12 , wherein the display panel further comprises a driving circuit region, the fan-out region is provided between the pixel region and the driving circuit region, the driving circuit region comprises first driving chips and second driving chips, after forming the second insulation layer, the method further comprises:
forming first via holes penetrating through the first insulation layer and the second insulation layer in the fan-out region, and forming second via holes penetrating through the second insulation layer in the fan-out region by patterning process, so that the first driving chip is electrically connected with the first signal lines through the first via holes, and the second driving chip is electrically connected with the second signal lines through the second via holes, the second via hole has a step-like inner wall, and each step is positioned at an interface between any two adjacent layers of structures in the second insulation layer.

16 . The method of claim 15 , wherein a diameter of a circle formed by each step increases sequentially along a direction away from the first insulation layer.

17 . The method of claim 14 , wherein thicknesses of the four layers of structures of the second insulation layer are sequentially in ranges of 10 nm to 50 nm, 50 nm to 500 nm, 50 nm to 500 nm and 10 nm to 50 nm along a direction away from the first insulation l

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Li Jing
• Cui Yulin

Classifications

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W20/082 Primary

  the openings being tapered via holes · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10D86/021

  of multiple TFTs · CPC title