Power semiconductor module with low inductance gate crossing

Patent metadata

Field	Value
Publication number	US-12068290-B2
Application number	US-202017611305-A
Country	US
Kind code	B2
Filing date	Apr 2, 2020
Priority date	May 14, 2019
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A power semiconductor module includes a main substrate and power semiconductor chips. Each power semiconductor chip is bonded to the main conductive layer with the first power electrode. A first group of the power semiconductor chips is connected in parallel via the second power electrodes and a second group of the power semiconductor chips is connected in parallel via the second power electrodes. The module also includes a first insulation layer and a first conductive layer overlying the first insulation layer as well as a second insulation layer and a second conductive layer overlying the second insulation layer. The first conductive layer provides a first gate conductor area and a first auxiliary emitter conductor area for the first group. The second conductive layer provides a second gate conductor area and a second auxiliary emitter conductor area for the second group.

First claim

The invention claimed is:

1. A power semiconductor module, comprising:
a main substrate with a main conductive layer separated into conductive areas;
a plurality of power semiconductor chips, wherein each power semiconductor chip has a first power electrode, a second power electrode, and a gate electrode, wherein each power semiconductor chip is bonded to the main conductive layer with the first power electrode and wherein a first group of the power semiconductor chips is connected in parallel via the second power electrodes and a second group of the power semiconductor chips is connected in parallel via the second power electrodes;
a first insulation layer attached to the main conductive layer;
a first conductive layer provided on the first insulation layer, wherein the first conductive layer provides a first gate conductor area electrically connected to the gate electrodes of the first group and a first auxiliary emitter conductor area electrically connected to power electrodes of the first group;
a second insulation layer attached to the first conductive layer; and
a second conductive layer provided on the second insulation layer, wherein the second conductive layer provides a second gate conductor area electrically connected to the gate electrodes of the second group and a second auxiliary emitter conductor area electrically connected to power electrodes of the second group;
wherein the main conductive layer, the first insulation layer, the first conductive layer, the second insulation layer and the second conductive layer are stacked with respect to each other.

2. The power semiconductor module of claim 1 ,
wherein the first gate conductor area and the second gate conductor area are stacked with each other; and
wherein the first auxiliary emitter conductor area and the second auxiliary emitter conductor area are stacked with each other.

3. The power semiconductor module of claim 1 , wherein the first auxiliary emitter conductor area is provided on both sides of the first gate conductor area and wherein the second auxiliary emitter conductor area is provided on both sides of the second gate conductor area.

4. The power semiconductor module of claim 1 ,
wherein the first conductive layer comprises a first elongated strip and the second conductive layer comprises a second elongated strip; and
wherein the first elongated strip and the second elongated strip run parallel to each other.

5. The power semiconductor module of claim 1 , further comprising a third conductive layer stacked with the first conductive layer and the second conductive layer, the third conductive layer providing third conductive areas.

6. The power semiconductor module of claim 1 , further comprising an intermediate conductive layer arranged between the first conductive layer and the second conductive layer, wherein the intermediate conductive layer is electrically floating.

7. The power semiconductor module of claim 1 ,
wherein the main conductive layer of the main substrate comprises a first control conductor area providing a part of a first control conductor;
wherein the first control conductor area is connected via at least one wirebond with the first conductive layer;
wherein the main conductive layer of the main substrate comprises a second control conductor area providing a part of a second control conductor; and
wherein the second control conductor area is connected via at least one wirebond with the second conductive layer.

8. The power semiconductor module of claim 1 , wherein the power semiconductor chips are arranged in parallel rows and the first conductive layer and the second conductive layer are arranged on a side of the rows and run orthogonal to the rows.

9. The power semiconductor module of claim 1 ,
wherein the power semiconductor chips of the first group are arranged in two parallel first rows and the power semiconductor chips of the second group are arranged in two second parallel rows, which are arranged between the first rows;
wherein first main layer gate conductor areas of the main conductive layer are arranged outside of the rows of semiconductor chips and are electrically connected to the first conductive layer; and
wherein a second main layer gate conductor area is arranged between the second rows of semiconductor chips and is electrically connected to the second conductive layer.

10. A power semiconductor module, comprising:
a main substrate with a main conductive layer separated into conductive areas;
a plurality of power semiconductor chips, wherein each power semiconductor chip has a first power electrode, a second power electrode, and a gate electrode, wherein each power semiconductor chip is bonded to the main conductive layer with the first power electrode, and wherein a first group of the power semiconductor chips is connected in parallel via the second power electrodes and a second group of the power semiconductor chips is connected in parallel via the second power electrodes;
a first insulation layer attached to the main conductive layer;
a first conductive layer provided on the first insulation layer, wherein the first conductive layer provides a first auxiliary emitter conductor area electrically connected to power electrodes of the first group and a second auxiliary emitter conductor area electrically connected to power electrodes of the second group;
a second insulation layer attached to the first conductive layer; and
a second conductive layer provided on the second insulation layer, wherein the second conductive layer provides a first gate conductor area electrically connected to the gate electrodes of the first group and a second gate conductor area electrically connected to the gate electrodes of the second group;
wherein the main conductive layer, the first insulation layer, the first conductive layer, the second insulation layer and the second conductive layer are stacked with respect to each other.

11. The power semiconductor module of claim 10 ,
wherein the first gate conductor area and the first auxiliary emitter conductor area are stacked with each other; and
wherein the second gate conductor area and the second auxiliary emitter conductor area are stacked with each other.

12. The power semiconductor module of claim 10 , wherein a third conductive layer provides a third auxiliary emitter conductor area electrically connected to the first auxiliary emitter conductor area and a fourth auxiliary emitter conductor area electrically connected to the second auxiliary emitter conductor area.

13. The power semiconductor module of claim 12 ,
wherein the first auxiliary emitter conductor area, the first gate conductor area and the third auxiliary emitter conductor area are stacked with each other; and
wherein the second auxiliary emitter conductor area, the second gate conductor area and the fourth auxiliary emitter conductor area are stacked with each other.

14. The power semiconductor module of claim 12 ,
wherein the main conductive layer comprises a main layer gate conductor area and two main layer auxiliary emitter conductor areas, which are arranged on two sides of the main layer gate conductor area;
wherein the main layer gate conductor area and one of the first and the second gate conductor area are electrically interconnected;
wherein the main layer auxiliary emitter conductor areas and one of the first and the second auxiliary emitter conductor areas are electrically interconnected; and
wherein the main layer gate conductor area and the third auxiliary emitter conductor area are arranged such that they face towards the one of the first and second gate conductor area and the

Assignees

• Hitachi Energy Ltd

Inventors

• Schroeder Arne
• Kicin Slavo
• Mohn Fabian
• Schuderer Juergen

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title