Semiconductor die being connected with a clip and a wire which is partially disposed under the clip

Patent metadata

Field	Value
Publication number	US-12068274-B2
Application number	US-202017110755-A
Country	US
Kind code	B2
Filing date	Dec 3, 2020
Priority date	Dec 5, 2019
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A semiconductor device includes a first carrier, a first external contact, a second external contact, and a first semiconductor die. The first semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The first semiconductor die is disposed with the first main face on the first carrier. A clip connects the second contact pad and the second external contact. A first wire is connected with the first external contact. The first wire is disposed at least partially under the clip.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first carrier;
a first external contact and a second external contact;
a first semiconductor die comprising a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor, the first semiconductor die being disposed with the first main face on the first carrier;
a clip connecting the second contact pad and the second external contact, the clip having a thick portion and a thin portion, the clip comprising a cavity formed by the thin portion; and
a first wire connected with the first external contact, the first wire being disposed completely under the cavity.

2. The semiconductor device of claim 1 , wherein the second contact pad is completely covered by the clip.

3. The semiconductor device of claim 1 , wherein the cavity is also disposed above a second wire.

4. The semiconductor device of claim 1 , further comprising:
a first insulation layer disposed on a portion of the clip which is disposed above the wire.

5. The semiconductor device of claim 4 , wherein the first insulation layer has the form of a rectangular strip, the rectangular strip being disposed above the wire.

6. The semiconductor device of claim 4 , wherein the first insulation layer has the form of a closed ring, the closed ring comprising a portion which is disposed above the wire.

7. The semiconductor device of claim 4 , further comprising:
a second carrier;
a second insulation layer disposed on the second carrier;
a second semiconductor die disposed on the second carrier, the second semiconductor die comprising at least one contact pad;
a third external contact; and
a second wire connected between the at least one contact pad and the third external contact,
wherein the second insulation layer is disposed below the second wire.

8. The semiconductor device of claim 4 , wherein the first insulation layer comprises one or more of a dielectric, an epoxy type dielectric, a foil, and a film.

9. The semiconductor device of claim 4 , wherein the first insulation layer comprises a thickness in a range from 2 μm to 100 μm.

10. The semiconductor device of claim 4 , further comprising:
an encapsulant disposed such that a main face of the clip that is remote from the first semiconductor die is exposed to the outside.

11. The semiconductor device of claim 1 , wherein the wire is connected between the third contact pad and the first external contact.

12. The semiconductor device of claim 1 , further comprising:
a second semiconductor die electrically connected with the clip and by the clip with the first semiconductor die.

13. The semiconductor device of claim 1 , further comprising:
a second semiconductor die comprising at least one contact pad,
wherein the wire is connected between the at least one contact pad and the first external contact.

14. The semiconductor device of claim 1 , further comprising:
an insulator body connected to a portion of the wire, wherein the insulator body is also connected to the second main face of the first semiconductor die.

15. The semiconductor device of claim 14 , wherein the insulator body is also connected to a side face of the first semiconductor die and to a main face of the first carrier.

16. The semiconductor device of claim 14 , wherein the insulator body comprises one or more of a dielectric, and an epoxy type dielectric.

17. The semiconductor device of claim 1 , further comprising:
an encapsulant, wherein
the clip comprises a main face remote from the semiconductor die,
wherein the encapsulant is disposed such that the main face is exposed to the outside.

18. The semiconductor device of claim 1 , further comprising:
an encapsulant,
wherein the clip comprises a main face remote from the semiconductor die,
wherein the encapsulant is disposed such that the main face is not exposed to the outside.

19. A semiconductor device, comprising:
a first carrier;
a first external contact and a second external contact;
a first semiconductor die comprising a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor, the first semiconductor die being disposed with the first main face on the first carrier;
a clip connecting the second contact pad and the second external contact, the clip having a thick portion and a thin portion, the clip comprising a cavity formed by the thin portion;
a first wire connected with the first external contact, the first wire being disposed completely under the cavity; and
a first insulation layer disposed on a portion of the clip which is disposed above the wire.

20. The semiconductor device of claim 10 , further comprising:
an encapsulant disposed such that a main face of the clip that is remote from the first semiconductor die is exposed to the outside.

Assignees

• Infineon Technologies Ag

Inventors

• Pavier Mark

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W72/871

  Bond wires and strap connectors · CPC title

• H10W72/076

  of strap connectors · CPC title

• H10W72/075

  of bond wires · CPC title