Capacitor in a three-dimensional memory structure

Patent metadata

Field	Value
Publication number	US-12068240-B2
Application number	US-202117461435-A
Country	US
Kind code	B2
Filing date	Aug 30, 2021
Priority date	Aug 31, 2020
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

Memory devices can be structured in a three-dimensional arrangement using a circuit under array (CUA) architecture. The memory array of such a memory device can include memory cells disposed in vertically arranged tiers. With the memory array extending over a substrate, the CUA region under the memory array can include control circuitry for the memory array. A space adjacent the memory array and disposed above the CUA region can include a dielectric material and conductive structures, with the conductive structures extending vertically in the dielectric material and alongside the memory array. The conductive structures separated by the dielectric material can be used as a capacitor coupled between nodes with the nodes configured to provide different voltages. This capacitor can be coupled to a circuit or a connection node below the level of the memory array.

First claim

What is claimed is:

1. A memory device comprising:
a memory array extending over a substrate in a memory die, the memory array including multiple vertically arranged tiers comprising memory cells;
a first region, in the memory die, under the memory array including control circuitry for the memory array; and
a second region, in the memory die, adjacent the memory array and disposed above the first region, the second region including:
dielectric material; and
conductive structures extending vertically in the dielectric material and alongside at least a portion of the memory array, the conductive structures separated by dielectric material and arranged to form a capacitor coupled between nodes configured to provide different voltages, at least two of the nodes being electrically isolated and separate from each other.

2. The memory device of claim 1 , wherein the dielectric material includes one or more materials.

3. The memory device of claim 1 , wherein the conductive structures are conductive plugs extending from a level at or below a bottom level of the memory array to a level at or above a top level of the memory array.

4. The memory device of claim 1 , wherein the memory device includes a third region next to the first region under the memory array such that the second region is directly above the third region.

5. The memory device of claim 4 , wherein the capacitor is coupled in the third region as part of a circuit in the third region.

6. The memory device of claim 1 , wherein the conductive structures are arranged in a pattern such that capacitance is provided by one or more pairs of conductive structures with the conductive structures of each pair coupled to different nodes that operatively couple the conductive structures of the pair to different voltages.

7. The memory device of claim 1 , wherein unit capacitance is provided by a fourth of each conductive structure of a set of four conductive structures of the conductive structures, with the set arranged such that conductive structures of the set arranged diagonally opposite each other are coupled to one or more nodes providing a voltage that is common to the diagonally opposite conductive structures.

8. The memory device of claim 1 , wherein the capacitor has a capacitance per unit area equal to or greater than about 1.55 fF/μm 2 .

9. The memory device of claim 1 , wherein each conductive structure is a metal conductive structure.

10. The memory device of claim 1 , wherein each conductive structure includes multiple metals with an outer region of the conductive structure having a metal that acts as a barrier preventing other metal within the conductive structures from diffusing into the dielectric material.

11. The memory device of claim 10 , wherein the metal that acts as a barrier includes titanium nitride and the other metal includes tungsten.

12. The memory device of claim 1 , wherein the dielectric material includes an electrically insulating oxide or an electrically insulating nitride.

13. A memory device comprising:
a memory array extending over a substrate in a memory die, the memory array including multiple vertically arranged tiers comprising memory cells;
a first region, in the memory die, under the memory array including control circuitry for the memory array;
a second region, in the memory die, adjacent the first region under the memory array and outside a horizontal extent of the memory array, the second region having pads to couple to the control circuitry;
a third region, in the memory die, adjacent the memory array and disposed above the second region, the third region including:
dielectric material; and
conductive structures extending vertically in the dielectric material and alongside at least a portion of the memory array, the conductive structures separated by dielectric material and arranged to form a capacitor; and
nodes coupled to the conductive structures such that the nodes are configured to operatively provide different voltages to selected ones of the conductive structures, at least two of the nodes being electrically isolated and separate from each other.

14. The memory device of claim 13 , wherein the conductive structures extend from a level at or below a bottom level of the memory array to a level at or above a top level of the memory array.

15. The memory device of claim 13 , wherein the conductive structures are arranged in a pattern such that capacitance is provided by one or more pairs of conductive structures with the conductive structures of each pair coupled to different nodes that operatively couple the conductive structures of the pair to different voltages.

16. The memory device of claim 13 , wherein unit capacitance is provided by a fourth of each conductive structure of a set of four conductive structures of the conductive structures, with the set arranged such that conductive structures of the set arranged diagonally opposite each other are coupled to one or more nodes providing a voltage that is common to the diagonally opposite conductive structures.

17. A method of forming a memory device, the method comprising:
forming a first region, in a substrate of a memory die, including control circuitry for a memory array;
forming the memory array over the first region, including forming the memory array having multiple vertically arranged tiers comprising memory cells;
forming a second region, in the memory die, adjacent the memory array and disposed above the first region, including forming dielectric material in the second region;
forming conductive structures, in the memory die, extending vertically in the dielectric material and alongside at least a portion of the memory array, with the conductive structures separated by portions of the dielectric material; and
coupling nodes, in the memory die, to the conductive structures such that the conductive structures and the dielectric material form a capacitor, at least two of the nodes formed being electrically isolated and separate from each other.

18. The method of claim 17 , wherein forming conductive structures includes:
forming vias in the dielectric material; and
forming conductive material in the vias.

19. The method of claim 18 , wherein forming vias includes etching the dielectric material and forming conductive material includes forming a conductive barrier on surfaces of each via and forming additional conductive material on and contacting each conductive barrier in each via.

20. The method of claim 17 , wherein forming the conductive structures includes forming the conductive structures arranged in a pattern such that capacitance is provided by one or more pairs of conductive structures with the conductive structures of each pair coupled to different ones of the nodes that operatively couple to different voltages.

Assignees

• Micron Technology Inc

Inventors

• Guo Xiaojiang
• Kaushik Naveen
• Xu Shuai
• Lee June

Classifications

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10D1/68 Primary

  Capacitors having no potential barriers · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/41 Primary

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title