Extension of nanocomb transistor arrangements to implement gate all around

Patent metadata

Field	Value
Publication number	US-12068206-B2
Application number	US-202017030449-A
Country	US
Kind code	B2
Filing date	Sep 24, 2020
Priority date	Sep 24, 2020
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

First claim

The invention claimed is:

1. A transistor arrangement, comprising:
a substrate;
a base comprising a face that is opposite the substrate, a first sidewall between the face and the substrate, and a second sidewall opposite the first sidewall;
a nanoribbon comprising a first semiconductor material and having a longitudinal axis substantially parallel to the substrate, where the base is between the substrate and the nanoribbon;
a gate insulator-wrapping around a portion of the nanoribbon between a first plane and a second plane, where each of the first plane and the second plane is substantially perpendicular to the longitudinal axis of the nanoribbon; and
an opening partially filled with a first insulator and partially filled with a second insulator, the opening extending in a direction substantially parallel to the longitudinal axis of the nanoribbon, wherein the second insulator is closer to the substrate than the first insulator and is etch selective with respect to the first insulator.

2. The transistor arrangement according to claim 1 , wherein:
the second sidewall of the base has a first portion and a second portion,
the second portion is between the substrate and the first portion, and
no portion of the second insulator is between the first portion of the second sidewall of the base and the first insulator.

3. The transistor arrangement according to claim 1 , wherein:
the second sidewall of the base has a first portion and a second portion,
the second portion is between the substrate and the first portion, and
a portion of the opening between a plane parallel to the substrate and aligned with a top of the first portion of the second sidewall of the base and a plane parallel to the substrate and aligned with a bottom of the first portion of the second sidewall of the base further includes a gate electrode material,
the transistor arrangement further includes the gate insulator between the first portion of the second sidewall of the base and the first insulator, and
the gate insulator that is between the first portion of the second sidewall of the base and the first insulator is between the first portion of the second sidewall of the base and the gate electrode material.

4. The transistor arrangement according to claim 3 , further comprising:
the gate insulator between the gate electrode material and the first insulator.

5. The transistor arrangement according to claim 1 , wherein:
the second sidewall of the base has a first portion and a second portion,
the second portion is between the substrate and the first portion,
the transistor arrangement further includes the gate insulator between the first portion of the second sidewall of the base and the first insulator, and
the gate insulator that is between the first portion of the second sidewall of the base and the first insulator has a first side that is in contact with the first portion of the second sidewall of the base and has a second side that is in contact with the first insulator.

6. The transistor arrangement according to claim 5 , wherein no portion of the opening between a plane parallel to the substrate and aligned with a top of the first portion of the second sidewall of the base and a plane parallel to the substrate and aligned with a bottom of the first portion of the second sidewall of the base includes a gate electrode material.

7. The transistor arrangement according to claim 1 , wherein:
the second sidewall of the base has a first portion and a second portion,
the second portion is between the substrate and the first portion, and
no portion of the gate insulator is between the second portion of the second sidewall of the base and the first insulator.

8. The transistor arrangement according to claim 1 , wherein:
the second sidewall of the base has a first portion, a second portion, and a third portion,
the second portion is between the substrate and the first portion,
the third portion is between the substrate and the second portion, and
a portion of the opening between a plane parallel to the substrate and aligned with a top of the third portion of the second sidewall of the base and a plane parallel to the substrate and aligned with a bottom of the third portion of the second sidewall of the base is filled with the second insulator.

9. The transistor arrangement according to claim 1 , wherein:
the second sidewall of the base has a first portion and a second portion,
the second portion is between the substrate and the first portion, and
a portion of the second insulator is between the second portion of the second sidewall of the base and the first insulator.

10. The transistor arrangement according to claim 9 , further comprising the gate insulator between the first portion of the second sidewall of the base and the first insulator.

11. A transistor arrangement, comprising:
a nanoribbon comprising a semiconductor material, the nanoribbon having a first face, a second face opposite the first face, a first sidewall between the first face and the second face, and a second sidewall opposite the first sidewall;
a gate stack over a portion of the nanoribbon, the gate stack comprising:
a gate insulator wrapping around a portion of the nanoribbon and having a portion at the second sidewall of the nanoribbon, and
a gate electrode material wrapping around the gate insulator; and

an insulator, shaped as a wall extending along the second sidewall of the nanoribbon,
wherein the portion of the gate insulator at the second sidewall of the nanoribbon is between, and in contact with, the semiconductor material of the nanoribbon and the insulator.

12. The transistor arrangement according to claim 11 , wherein:
the nanoribbon is one of a plurality of nanoribbons stacked above one another,
the gate electrode material wrapping around the gate insulator wrapping around the portion of different nanoribbons of the plurality of nanoribbons is electrically continuous among the different nanoribbons of the plurality of nanoribbons,
the insulator extends along the second sidewall of the different nanoribbons of the plurality of nanoribbons, and
for each nanoribbon of the plurality of nanoribbons, the portion of the gate insulator at the second sidewall of the nanoribbon is between, and in contact with, the semiconductor material of the nanoribbon and the insulator.

13. An integrated circuit (IC) structure, comprising:
a plurality of nanoribbons stacked over one another;
a gate insulator wrapping around portions of different nanoribbons of the plurality of nanoribbons;
a gate electrode material wrapping around the gate insulator wrapping around the portions of the different nanoribbons of the plurality of nanoribbons;
an insulator structure extending substantially vertically and along sidewalls of the plurality of nanoribbons; and
a layer of the gate insulator at a sidewall of the insulator structure that is closest to the sidewalls of the plurality of nanoribbons.

14. The IC structure according to claim 13 , wherein the layer of the gate insulator at the sidewall of the insulator structure is in contact with an insulator material of the insulator structure.

15. The IC structure according to claim 14 , wherein the layer of the gate insulator at the sidewall of the insulator structure is further in contact with the different nanoribbons of the plurality of nanoribbons.

16. The IC structure according to claim 14 , wherein the layer of the gate insulator at the sidewall of the insulator structure is further in contact with the gate electrode material wrapping around the gate insulator wrapping

Assignees

• Intel Corp

Inventors

• Mishra Varun
• Cea Stephen M
• Weber Cory E
• Kavalieros Jack T
• Ghani Tahir

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title