Method for fabricating semiconductor structure

Patent metadata

Field	Value
Publication number	US-12068158-B2
Application number	US-202117474067-A
Country	US
Kind code	B2
Filing date	Sep 14, 2021
Priority date	Apr 23, 2021
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

Embodiment relates to a method for fabricating a semiconductor structure. The method includes: forming a first pattern on the first region and forming a second pattern on the second region, wherein the first pattern includes a plurality of first sub-patterns, a first gap is provided between adjacent two of the plurality of first sub-patterns, a width of the first gap is a first pitch, and wherein the second pattern includes a plurality of second sub-patterns, a second gap is provided between adjacent two of the plurality of second sub-patterns, a width of the second gap is a second pitch, and the second pitch is greater than the first pitch; forming a first mask layer on a sidewall of the first pattern, and forming a second mask layer on a sidewall of the second pattern; and removing the first pattern and the second pattern.

First claim

What is claimed is:

1. A method for fabricating a semiconductor structure, the semiconductor structure comprising a first region and a second region adjacent to each other, the method comprising:
forming a first pattern on the first region and forming a second pattern on the second region, the first pattern comprising a plurality of first sub-patterns, a first gap being provided between adjacent two of the plurality of first sub-patterns, a width of the first gap being a first pitch, the second pattern comprising a plurality of second sub-patterns, a second gap being provided between adjacent two of the plurality of second sub-patterns, a width of the second gap being a second pitch, the second pitch being greater than the first pitch;
forming a first mask layer on a sidewall of the first pattern, and forming a second mask layer on a sidewall of the second pattern, the first mask layer filling up the first gap, and the second mask layer not filling up the second gap;
removing the first pattern and the second pattern;
forming a mask pattern layer, the mask pattern layer covering a top and the sidewall of the first pattern and filling up the first gap, the mask pattern layer covering a top and the sidewall of the second pattern and a bottom of the second gap, a third gap being provided between each of the plurality of first sub-patterns and each of the plurality of second sub-patterns adjacent to each other, and the mask pattern layer also covering a bottom of the third gap; and
removing the mask pattern layer at the top of the first pattern, removing the mask pattern layer at the top of the second pattern and the mask pattern layer at the bottom of the second gap, and removing a portion of the mask pattern layer at the bottom of the third gap, to form the first mask layer in the first region and form the second mask layer in the second region; and,
wherein before removing the mask pattern layer at the top of the first pattern, removing the mask pattern layer at the top of the second pattern and the mask pattern layer at the bottom of the second gap, and removing a portion of the mask pattern layer at the bottom of the third gap, and the method further comprises:
reducing a thickness of the mask pattern layer, such that the thickness of the second mask layer is a target thickness, wherein the thickness of the mask pattern layer is reduced by means of a wet etching process.

2. The method for fabricating a semiconductor structure according to claim 1 , wherein a thickness of the mask pattern layer is a first thickness, the first pitch being less than twice the first thickness, and the second pitch being greater than twice the first thickness.

3. The method for fabricating a semiconductor structure according to claim 1 , wherein a mask pattern material layer is deposited several times to obtain the mask pattern layer, a thickness of the mask pattern material layer deposited each time being a second thickness, and both the first pitch and the second pitch being greater than twice the second thickness.

4. The method for fabricating a semiconductor structure according to claim 1 , wherein the mask pattern layer is formed by means of an atomic layer deposition process.

5. The method for fabricating a semiconductor structure according to claim 1 , wherein the mask pattern layer comprises an oxide layer.

6. The method for fabricating a semiconductor structure according to claim 1 , wherein the forming a first pattern on the first region and forming a second pattern on the second region comprise:
forming a photoresist layer on the first region and the second region; and
patterning the photoresist layer to form the first pattern on the first region and form the second pattern on the second region.

7. The method for fabricating a semiconductor structure according to claim 1 , wherein before the forming a first pattern on the first region and forming a second pattern on the second region, the method further comprises:
providing a stacked structure; and
after the removing the first pattern and the second pattern, the method further comprises:
patterning the stacked structure based on the first mask layer and the second mask layer to obtain a target structure.

8. The method for fabricating a semiconductor structure according to claim 7 , wherein the stacked structure comprises a first dielectric layer, a hard mask layer and a second dielectric layer stacked from bottom to top, the first pattern and the second pattern both being positioned above the second dielectric layer; and
the patterning the stacked structure based on the first mask layer and the second mask layer comprises: patterning the second dielectric layer and the hard mask layer based on the first mask layer and the second mask layer.

9. The method for fabricating a semiconductor structure according to claim 8 , wherein the first dielectric layer and the second dielectric layer both comprise a silicon oxynitride layer, the hard mask layer comprising a carbon layer.

10. The method for fabricating a semiconductor structure according to claim 7 , wherein the target structure comprises a first target structure positioned in the first region and a second target structure positioned in the second region, the first target structure comprising a plurality of first target substructures, the second target structure comprising a plurality of second target substructures, and number of the plurality of second target substructures being greater than that of the plurality of first target substructures.

11. The method for fabricating a semiconductor structure according to claim 1 , wherein the first mask layer comprises a plurality of third sub-patterns, a fourth gap being provided between adjacent two of the plurality of third sub-patterns, a width of the fourth gap being a fourth pitch, the second mask layer comprising a plurality of fourth sub-patterns, a fifth gap being provided between adjacent two of the plurality of fourth sub-patterns, a width of the fifth gap being a fifth pitch, the fifth pitch being greater than the fourth pitch, and after removing the first pattern and the second pattern, the method further comprising:
forming a third mask layer on a sidewall of the first mask layer, and forming a fourth mask layer on a sidewall of the second mask layer, the third mask layer filling up the fourth gap, and the fourth mask layer not filling up the fifth gap; and
removing the first mask layer and the second mask layer.

12. The method for fabricating a semiconductor structure according to claim 11 , wherein before forming a first pattern on the first region and forming a second pattern on the second region, the method further comprises:
providing a stacked structure; and
after removing the first mask layer and the second mask layer, the method further comprises:
patterning the stacked structure based on the third mask layer and the fourth mask layer to obtain a target structure.

13. The method for fabricating a semiconductor structure according to claim 1 , wherein the first mask layer comprises a plurality of third sub-patterns, a fourth gap being provided between adjacent two of the plurality of third sub-patterns, the second mask layer comprising a plurality of fourth sub-patterns, a fifth gap being provided between adjacent two of the plurality of fourth sub-patterns, and after removing the first pattern and the second pattern, the method further comprising:
forming a fifth mask layer on a sidewall of the first mask layer and forming a sixth mask layer on a sidewall of the second mask layer, the fifth mask layer not filling up the fourth gap, and the sixth mask layer not filling up the fifth gap; and
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Assignees

• Changxin Memory Tech Inc

Inventors

• Zhan Kangshu
• Wan Qiang
• Xu Penghui
• Liu Tao
• Li Sen
• Xia Jun

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P76/405 Primary

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H01L21/31144

  Electricity · mapped topic

• H01L21/0332 Primary

  Electricity · mapped topic