Fin field-effect transistor (FinFET) based semiconductor memory array having memory cells using a reduced surface area

Patent metadata

Field	Value
Publication number	US-12068027-B2
Application number	US-202217890290-A
Country	US
Kind code	B2
Filing date	Aug 18, 2022
Priority date	Aug 18, 2022
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A fin field-effect transistor (FinFET) based semiconductor memory array having a plurality of memory cells, each memory cell including a write transistor having a write wordline gate over a first fin connected to a write wordline gate contact, a write bitline contact in connection with the first fin, and a storage node contact in connection with the first fin, and a read transistor having a storage node gate over a second fin, the storage node gate connected to a storage node gate contact, the storage node gate contact connected to the storage node contact, a read wordline contact in connection with the second fin, and a read bitline contact in connection with the second fin, wherein the write wordline gate and the storage node gate are arranged in series to each other along an extension axis that coincides with an longitudinal axis of the write wordline gate and a longitudinal axis of the storage node gate.

First claim

The invention claimed is:

1. A fin field-effect transistor (FinFET) based semiconductor memory array ( 300 ) having a plurality of memory cells ( 100 ), each memory cell ( 100 ) comprising:
a write transistor ( 10 ) having a write wordline (WWL) gate in connection with a first fin ( 15 ) connected to a write wordline (WWL) gate contact, a write bitline (WBL) contact in connection with the first fin ( 15 ), and a storage node (SN) contact in connection with the first fin ( 15 ); and
a read transistor ( 20 ) having a storage node (SN) gate in connection with a second fin ( 25 ), the storage node (SN) gate connected to a storage node (SN) gate contact, the storage node (SN) gate contact connected to the storage node (SN) contact, a read wordline (RWL) contact in connection with the second fin ( 25 ), and a read bitline (RBL) contact in connection with the second fin ( 25 ),
wherein the write wordline (WWL) gate and the storage node (SN) gate are arranged in series to each other along an extension axis that coincides with a longitudinal axis of the write wordline (WWL) gate and a longitudinal axis of the storage node (SN) gate.

2. The FinFET transistor based semiconductor memory array ( 300 ) according to claim 1 , wherein the write wordline (WWL) gate is not arranged to be in connection with the second fin ( 25 ), and the storage node (SN) gate is not arranged to be in connection the first fin ( 15 ).

3. The FinFET transistor based semiconductor memory array ( 300 ) according to claim 1 , each memory cell further comprising:
a dummy gate ( 30 ) extending to be in connection with both the first fin ( 15 ) and the second fin ( 25 ), arranged to be in parallel with the extension axis, the dummy gate ( 30 ) shared with a neighboring memory cell in a same memory cell column.

4. The FinFET transistor based semiconductor memory array ( 300 ) according to claim 3 , each memory cell further comprising:
a third fin ( 35 ) extending next to and in parallel to the first fin ( 15 ), the dummy gate ( 30 ), the storage node (SN) gate contact, the write wordline (WWL) gate, and the write bitline (WBL) contact in connection with the third fin ( 35 ).

5. The FinFET transistor based semiconductor memory array ( 300 ) according to claim 3 , each memory cell further comprising:
a fourth fin ( 45 ) extending next to and in parallel to the second fin ( 25 ), the dummy gate ( 30 ), the read wordline (RWL) contact, and the storage node (SN) gate in connection with the third fin ( 35 ).

6. The FinFET transistor based semiconductor memory array ( 300 ) according to claim 3 , each memory cell further comprising:
a third fin ( 35 ) extending next to and in parallel to the first fin ( 15 ), the dummy gate ( 30 ), the storage node (SN) gate contact, the write wordline (WWL) gate, and the write bitline (WBL) contact in connection with the third fin ( 35 ); and
a fourth fin ( 45 ) extending next to and in parallel to the second fin ( 25 ), the dummy gate ( 30 ), the read wordline (RWL) contact, and the storage node (SN) gate in connection with the third fin ( 35 ).

7. The FinFET transistor based semiconductor memory array ( 300 ) according to claim 1 , wherein the write bitline (WBL) contact, the first fin ( 15 ), the read bitline (RBL) contact, and the second fin ( 25 ) are shared by a same neighboring memory cell of a corresponding memory cell column.

8. A fin field-effect transistor (FinFET) based semiconductor memory array ( 300 ) having a plurality of memory cells ( 200 ), each memory cell ( 200 ) comprising:
a write transistor ( 110 ) having a write wordline (WWL) gate in connection with a first fin ( 115 ) connected to a write wordline (WWL) gate contact, a write bitline (WBL) contact in connection with the first fin ( 115 ), and a storage node (SN) contact in connection with the first fin ( 115 );
a read transistor ( 120 ) having a storage node (SN) gate over the first fin ( 115 ), the storage node (SN) gate connected to a storage node (SN) gate contact, the storage node (SN) gate contact connected to the storage node (SN) contact, a read wordline (RWL) contact in connection with the first fin ( 115 ), and a read bitline (RBL) contact in connection with the first fin ( 115 ); and
a dummy gate ( 130 ) extending to be in connection with the first fin ( 115 ),
wherein the write wordline (WWL) gate, the storage node (SN) gate, and the dummy gate ( 130 ) are arranged to be in parallel to each other.

9. The FinFET based semiconductor memory array ( 300 ) according to claim 8 , wherein the dummy gate ( 130 ) is arranged between the storage node (SN) gate of the read transistor ( 120 ) and the write wordline (WWL) gate of the write transistor ( 110 ).

10. The FinFET based semiconductor memory array ( 300 ) according to claim 8 , each memory cell further comprising:
a second fin ( 125 ) extending next to and in parallel to the first fin ( 115 ),
wherein the read bitline (RBL) contact, the storage node (SN) gate, read wordline (RWL) contact, the dummy gate ( 130 ), the storage node (SN) contact, the write wordline (WWL) gate, and the write bitline (WBL) are also contact in connection with the second fin ( 125 ).

11. The FinFET transistor based semiconductor memory array ( 300 ) according to claim 8 , wherein at least one of the storage node (SN) gate, the dummy gate ( 130 ), and/or the write wordline (WWL) gate are shared by a same neighboring memory cell of a corresponding memory cell row.

12. The FinFET transistor based semiconductor memory array ( 300 ) according to claim 8 , wherein the first fin ( 115 ) is continuous and shared by memory cells arranged in a same memory cell column of the memory cell ( 200 ).

13. The FinFET transistor based semiconductor memory array ( 300 ) according to claim 1 , wherein the read transistor ( 10 ) and the write transistor ( 20 ) each include one of a N-type channel or a P-type channel.

14. The FinFET transistor based semiconductor memory array according to claim 8 , wherein the read transistor ( 110 ) and the write transistor ( 120 ) each include one of a N-type channel or a P-type channel.

15. The FinFET transistor based semiconductor memory array ( 300 ) according to claim 1 , wherein the read transistor ( 10 ) and the write transistor ( 20 ) are configured for one of a high threshold voltage, regular threshold voltage, or low threshold voltage.

16. The FinFET transistor based semiconductor memory array ( 300 ) according to claim 8 , wherein the read transistor ( 110 ) and the write transistor ( 120 ) are configured for one of a high threshold voltage, regular threshold voltage, or low threshold voltage.

17. A fin field-effect transistor (FinFET) based memory cell ( 100 ) comprising:
a write transistor ( 10 ) having a write wordline (WWL) gate in connection with a first fin ( 15 ) connected to a write wordline (WWL) gate contact, a write bitline (WBL) contact in connection with the first fin ( 15 ), and a storage node (SN) contact in connection with the first fin ( 15 ); and
a read transistor ( 20 ) having a storage node (SN) gate in connection with a second fin ( 25 ), the storage node (SN) gate connected to a storage node (SN) gate contact, the storage node (SN) gate contact connected to the storage node (SN) contact, a read wordline (RWL) contact in connection with the second fin ( 25 ), and a read bitline (RBL) contact in connection with the second fin ( 25 ),
wherein the write wordline (WWL) gate and the storage node (SN) gate are arranged in series to each other along an extension axis that coincides with a longitudinal axis of the write wordline (WWL) gate a

Assignees

• Ecole Polytechnique Fed Lausanne Epfl

Inventors

• Giterman Robert
• Burg Andreas
• Yigit Halil Andac

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• H10B10/12

  comprising a MOSFET load element · CPC title